四位静态数码管控制器，含详细的中文注释，ＶＥＲＩＬＯＴ源码．...

here is realized simple FIFO stack in vhdl. very simple example, but very helpful.

最近在做毕设，ldpc码的编解码实现，这个是verilog实现。(Recently completed the set up to do, ldpc code codec implementation, this is the Verilog implementation.)

利用FPGA开发软件 进行rs编码的仿真 模拟RS编码的过程步骤(rs code in FPGA)

基于FPGA的出租车计价器，欢迎大死同学多多交流(FPGA-based Taximeter, welcomes the dead students more exchanges)

LFSR模块，单个模块，实现移位寄存器，生成测试用pattern-LFSR

用verilog语言编写的4位算术逻辑单元ALU,功能参考74181，包含.v文件以及测试用.vwf文件-Verilog languages with four arithmetic logic unit ALU, functional reference to 74,181, including. V documents and testing. Vwf document

说明：  高斯最小频移键控（Gaussian Filtered Minimum Shift Keying），这是GSM系统采用的调制方式。数字调制解调技术是数字蜂窝移动通信系统空中接口的重要组成部分。GMSK调制是在MSK（最小频移键控）调制器之前插入高斯低通预调制滤波器这样一种调制方式。GMSK提高了数字移动通信的频谱利用率和通信质量。(Gauss Filtered Minimum Shift Keying is a modulation method used in GSM system. Digital modem technology is an important part of air interface of digital cellular mobile communication system. GMSK modulation is a method of inserting a Gaussian low-pass pre-modulation filter before the MSK (minimum frequency shift keying) modulator. GMSK improves the spectrum utilization and communication quality of digital mobile communication.)

half band filter code

参数可配置的sequential 乘法器和booth 乘法器(verilog source code with configurable parameters for sequential multiplier and booth multiplier )

异步FIFO 输入: 16bit 输出:16bit 深度:256(Asynchronous FIFO Input: 16bit Output: 16bit Depth: 256)