四位静态数码管控制器，含详细的中文注释，ＶＥＲＩＬＯＴ源码．...

protel中fpga封装库2，非常难找的-protel library 2 in fpga package, very difficult to find the

Simple ALU Objectives 1. Explore simple ALU structure. 2. Working with components 3. Working with language templates in ModelSim 4. Making a test bench and simulation using ModelSim

说明：  能实现输入0.5 1 5块钱的累加，然后对应购买的商品价格进行比较，显示找的钱数或错误灯(MY English is very good)

说明：  fpga版本的数码管动态扫描程序，可供学习(FPGA version of the digital tube dynamic scanning program for learning)

说明：  this file describes the steps in building a fifo buffer module in verilog hdl and programming them on an fpga device

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ladder IS PORT(clk,reset:IN STD_LOGIC;

wm8731的使用，用于音频信号的采集或者产生(wm8731 use for audio signal acquisition or produce)

基于ＦＰＧＡ平台，实现了直接数字频率合成。-FPGA-based platform, to achieve a direct digital frequency synthesis.

hdlc协议的相关程序，用verilog语言编写，供大家交流学习(hdlc protocol procedures using Verilog language for the exchange of learning)

一位加法全加器，可以实现低位进位输入和高位进位输出。(full adder)