阶梯波程序

A simple Manchester Encoder to convert serial data to Manchester encoded data.

在MATLAB下自编实现快速傅里叶分析，(Fast fft own procedures, faster than the system call fft slowe)

高速FIFO，verilog设计。速度高达130Mhz-High-speed FIFO, verilog design. Speed up to 130MHz

multisim 程序 使用教程 详细明了清楚(multisim tutorial program uses more clearly understand)

8051参考设计，与其他8051的免费IP相比，文档相对较全，Oregano System 提供-8051 reference design, and other free IP in 8051 compared to relatively entire document, Oregano System for

基于verilog的LU分解,本文件包括详细的程序代码，运行文件，以及详细的文档(LU decompose based on verilog)

iic 总线 verilog 源代码 标准i2c总线， 有sda scl 时钟，频率自定(IIC bus standard Verilog source code i2c bus, has sda scl clock, the frequency of self-)

记忆是目前在大比例的所有数字系统中数字计算机的主要组成部分。记忆是征收流转税的二进制存储单元能够存储的二进制信息。除了这些细胞，内存包含用于存储 andretrieving 信息的电子线路。从内存中的 0 和 1 的形式，可以检索的信息。半导体存储器通常被认为是数字逻辑系统设计中的 mostvital 微电子组件。Semiconductormemories 的特点作为挥发物和不挥发物的内存设备。

设计制作一个可容纳4组参赛者的数字智力抢答器，每组设置一个抢答按键； 电路具有一第一抢答信号的鉴别和锁存的功能。在主持人将系统复位并发出抢答指令后，若参加者按抢答键，则该组指示灯亮并用组别显示抢答者的组别。此时，电路具有自锁功能，使别组的抢答开关不起作用。 设置计分电路。每组在开始时预置成6分，抢答后主持人计分，答对一次加1分。(The design can accommodate a the Entrants digital intellectual Responder, each set answer in a key circuit has a first answer in the signal to identify and latch functions. Host to the system reset and sent the answer in instruction, participants answer in key, the group of the group light and display the answer in the group. At this point, the circuit has a self-locking function does not work in other groups to answer switch. Set Scoring circuit. Preset six points each at the beginning of the answer in scoring after the host, answer time, add 1 point.)

说明：  this file describes the steps in building a fifo buffer module in verilog hdl and programming them on an fpga device