基于 FPGA 的乒乓游戏

FPGA来实现数据采集，AD采用TI公司的THS1206，高速并行AD，内含16字FIFO，降低硬件复杂度。(FPGA to realize data acquisition, AD using TI company s THS1206, high-speed parallel AD, containing the 16-character FIFO, to reduce hardware complexity.)

介绍了FPGA设计的十大准则，对初学者很有用，对于工作多年的同志，也会有整理总结的好处-Describes the FPGA design of the top ten criteria are useful for beginners, for many years comrades, there will be finishing the benefits of the summary

四线电阻式触摸屏，ads7846控制显示触摸坐标(Four-wire Resistive Touch Panel, ads7846 touch control display coordinates)

数字密码锁的vhdl实现，包括设置密码，修改密码，报警。

VHDL实现ALU的源代码，并且提供了一个详细的testbench！-ALU VHDL source code, and provide a detailed testbench!

说明：  数字示波器实验，利用AD、DA和VGA三个外设来实现简易示波器，DA外设发送正弦波给AD外设，AD外设解析成数字信号将数据送给VGA外设进行显示。在VGA上可以看到DA外设发送的波形、波形频率和波形峰峰值。(In the experiment of digital oscilloscope, AD, DA and VGA are used to realize simple oscilloscope. DA peripheral transmits sine wave to AD peripheral. AD peripheral resolves into digital signal and sends data to VGA peripheral for display. The waveform, waveform frequency and peak value of DA peripheral can be seen on VGA.)

这是我上大三时的电子设计题目，叫秒表的功能实现。利用ISE软件进行编程，代码是VHDL语言的，可以实现时（0-9）分（0-59）秒（0-59）即最大10小时的计数，对于不同开发板，可以适当修改代码，使之成为更加广泛的计数器。代码纯原创，请下载。

浅显易懂的vrilogHDL的程序，可以帮助你迅速上手-Easy and simple VerilogHDL programs to help you to get to the language quickly.

Verilog HDL教程 什么是Verilog HDL？ Verilog HDL 硬件描述语言(What is a Verilog HDL tutorials Verilog HDL? Verilog HDL hardware description language)

基于FPGA的八位RISC CPU的设计-FPGA-based RISC CPU design eight ....