FREEDEV数字应用开发板上的I2C总线IP核的verilog描述

采用FPGA实现的DDS波形发生器源码，可以实现频率幅值变换、正弦波、方波、三角波输出，输出频率可达1MHz(FPGA implementation of the DDS waveform generator source frequency amplitude transform, sine wave, square wave, triangle wave output, the output frequency up to 1MHz)

DDS中的正余弦生成，初始相位相差90度，可自行改变输出频率(Cosine generation of DDS, the initial phase difference of 90 degrees, the output frequency can be changed on their own)

vhdl,十进制加减计数器，输出计数序列信号-vhdl, decimal addition and subtraction counter, the output count sequence signal

BT656 时序, 逐行, 分辨率1280*960@25Hz(BT656 time series, row by row, resolution 1280*960@25Hz)

说明：  ad9649的fpga驱动程序,FMC接口，基于Xilinx KC705(AD9649 Evaluation Board, FMC Interposer & Xilinx KC705 Reference Design)

是一个用vhdl语言编写的pwm程序，可以方便地用来和nios连接，实现对nios的功能扩展。-is a VHDL language with the PWM procedures can be used to facilitate connections and nios, nios to achieve a functional extension.

VHDL的基本语法，应用，建模，编程示例等...(Introduction to VHDL basic syntax, applications, modeling, programming example and so on ...)

说明：  分数时延FIR滤波器FPGA设计的相关资料及软件无线电实验平台MFSS6842使用说明(Fractional delay FIR filter FPGA design related information and software radio experimental platform MFSS6842 instructions)

基于DE2开发板的VGA显示模块，仅供大家参考(DE2 development board based on the VGA display module, for your reference)

基于FPGA的DDS信号源设计，32位相位累加器，产生可调频率(FPGA-based DDS signal source design, 32-bit phase accumulator to generate tunable frequency)