KEY SCAN VHDL

基于FPGA的数字钟的设计，外部时钟32MHz，通过分频器得到秒脉冲，用于正常工作时的计数脉冲。通过分频还得到一个5ms的脉冲，用于按键的消抖（具体原理可见程序）。输入的信号有三个：1.时钟信号2.校时模式设置按键3.校时调整按键，输出通道6位数码管。共有：校时模块，24计数的小时计数模块，60计数的分钟计数模块，60计数的秒钟计数模块。

这是一篇介绍用verilog语言实现viterbi译码和rake接收机的文章，实用性很强的，在这里也感谢这篇文章的作着-This is a description language with verilog viterbi decoding and rake receiver of the article, very practical, here are grateful for this article was

Great guide for writing VHDL

通过本文章的学习能够使我们设计一些简单的逻辑电路和系统。很快我们就能过渡到设计相当复杂的数字逻辑系统。-To learn through this article, will enable us to design some simple logic circuits and systems. Soon we will be able to transition to the design of complex digital logic systems.

Blessing_3_v3_9_6稳定盈利set，仅限AUDNZD货币对，周期M1。 使用本压缩包内的SET，LAF默认是15，根据历史测试来看具有较大的风险，需要手动规避数据。 合理设置为LAF=8，请自行设置和调试，找到自己合适的风险值。 (Blessing_3_v3_9_6 stable profit set, only AUDNZD currency pairs, cycle M1. Use this package in the SET, the default is 15 fans, according to the angles of history test has great risk, need to avoid data manually. Reasonable set to fans = 8, please make your own setting and debugging, find their proper risk value.)

利用LPM_MUIT宏模块设计一个四位数据乘法器(Use LPM_MUIT macro module design a four data Multiplier)

基于verilog的FIR滤波器程序设计（调试过的）-verilog

说明：  资料的内容是实现旋转机械同步整周期采样的数据采集系统相关文献资料，包括鉴相信号如何倍频，机械振动信号相位如何检测等的实现方法。(Information content is for rotating mechanical synchronization synchronous sampling data acquisition system-related documents, including the Kam-believe number to harmonic mechanical vibration signal phase to detection of realization.)

16位有符号和无符号乘法器FPGA源代码(16-bit signed and unsigned multiplier FPGA source code)

AD73311芯片的控制和数据程序，用于控制音频AD芯片。(AD73311 chip control and data program)