登录
首页 » VHDL » PS2键盘控制程序实验的内容是用EDK建一个简单的系统并加入自定义的外设(一个ps2键盘控制器) 当键盘按下时会有相应的键扫描码输出显示到PC终端...

PS2键盘控制程序实验的内容是用EDK建一个简单的系统并加入自定义的外设(一个ps2键盘控制器) 当键盘按下时会有相应的键扫描码输出显示到PC终端...

于 2022-03-26 发布 文件大小:4.89 kB
0 157
下载积分: 2 下载次数: 1

代码说明:

PS2键盘控制程序实验的内容是用EDK建一个简单的系统并加入自定义的外设(一个ps2键盘控制器) 当键盘按下时会有相应的键扫描码输出显示到PC终端 -PS2 keyboard to control the content of the experimental procedure is used EDK build a simple system and add custom peripherals (a ps2 keyboard controller) when the keyboard is pressed the corresponding button will scan code to the PC terminal output shows

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • hssdrc IP核的可配置的通用SDRAM控制器的自适应银行…
    HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is licensed under MIT License
    2022-09-20 22:10:03下载
    积分:1
  • keyscan
    用verilog语言写的简单的键盘扫描代码,适合初学者,用alter的软件编写的程序代码。(Using verilog language to write simple keyboard scan code, suitable for beginners, with alter software program written code.)
    2013-09-13 22:59:11下载
    积分:1
  • clock
    EDA用maxplus2开发设计的简易数字钟,适合初学者,vhdL语言(EDA maxplus2 in development and design of simple digital clock, is suitable for beginners, vhdL language )
    2011-10-03 20:50:23下载
    积分:1
  • FXY
    说明:  FPGA做波形发生器,产生8种波形,包括三角波,正弦波,锯齿波,方波等。(FPGA is used as waveform generator,Generate 8 waveforms, including triangle, sine, sawtooth, square, etc.)
    2019-07-16 16:01:45下载
    积分:1
  • dds_vhdl
    DDS的VHDL程序,相当好,值得下载,共享才是王道(DDS, VHDL program is quite good, worth downloading, sharing is king)
    2012-06-03 22:52:55下载
    积分:1
  • ad7667.hdl
    自己编写的AD7667的数据采集程序,因为之前没用过,首次写!
    2022-02-28 09:44:00下载
    积分:1
  • 步进电机位置系统 步进电机位置系统block symbol file 步进电机位置系统的Verilog HDL程序设计 已编译通过
    步进电机位置系统 步进电机位置系统block symbol file 步进电机位置系统的Verilog HDL程序设计 已编译通过-Stepper motor stepper motor position location system system block symbol file location stepper motor system Verilog HDL program design has been compiled through
    2022-04-25 13:54:32下载
    积分:1
  • shift_regeister
    用blockram实现移位寄存器,开发语言为verilog hdl(Shift register with blockram achieve the development language for the verilog hdl)
    2020-08-13 22:18:29下载
    积分:1
  • altera niosii SOPC helloword learning
    altera niosii SOPC helloword 学习-altera niosii SOPC helloword learning
    2022-10-30 21:55:03下载
    积分:1
  • 11 阶FIR 数字滤波器,verolog描述,通过modelsim 6.0 仿真,Quartue综合...
    11 阶FIR 数字滤波器,verolog描述,通过modelsim 6.0 仿真,Quartue综合-11-order FIR digital filter, verolog description, modelsim 6.0 through simulation, Quartue integrated
    2022-10-31 17:45:02下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载