以前在学校里的课程设计，使用verilog编写的一个CPU程序，可以下板子...

说明：  模拟交通灯 verilog CPLD EPM1270 源代码(Simulation of traffic lights verilog CPLDEPM1270 source code)

说明：  verilog语言编写的dac5687的接口程序，串行模式控制。(written dac5687 verilog interface program, serial mode control.)

利用verilog HDL逐点比较法实现直线和圆弧插补(Use verilog HDL by-point comparison method to achieve linear and circular interpolation)

verilog编写的全功能串口-verilog programme of serial port

Used for Time shifting discrete signals, it can do both integral and fractional sampling period delay. Original.

利用VHDL语言实现PID控制,已经过调试验证。(Using VHDL language to implement PID control)

BulkIn是FPGA向CY7C68013发送数据 BulkOut是FPGA从CY7C68013接收数据,可以用LED显示 -BulkIn is the FPGA to the CY7C68013 is BulkOut send data CY7C68013 receive data from the FPGA, you can use LED display

步进电机驱动，32等级速度，带加减速度控制。verilog编写。(step motor driver,32 level speed.)

高速高性能FFT处理器的VLSI实现研究，适合做FPGA的技术人员参考研究FFT-High-speed high-performance FFT processor VLSI realization of research, suitable for FPGA technology reference study FFT

VHDL实现 DDS。大家共享吧，一起学习，一起进步(VHDL realize DDS. U.S. to share it with learning, with progress)