vhdl,序列信号检测模块，此模块检测1110010，可改为任意序列，输出电位为1为检测出，否则为0...

verilog写的LnE算法，可用于计算指数和对数(Verilog written in LnE algorithm, can be used to calculate the index and the logarithm)

针对32位MIPS微处理器中CLZ指令（对单个字高位连零进行计数）的实现电路，使用了类似于超前进位的逻辑结构。包含测试文档，以及Design Compile所用的环境和脚本。(The CLZ instruction counts the number of leading zeros in a word. The 32-bit word in the GPR rs is scanned from most-significant to least-significant bit.The number of leading zeros is counted and the result is written to the GPR rd. If all 32 bits are cleared in the GPR rs, the result written to the GPR rd is 32. )

fpga code for pong game

用FPGA分频，做一个有时分秒的时钟，并用数码管显示(FPGA divide a sometimes every minute clock, and digital display)

说明：  basys3的数字钟，可以显示00.00-59.59(Digital clock of basys3,It can display 00.00-59.59)

完成ITUR656标准的视频流数据向RGB格式的转换。-Complete video streaming ITUR656 standard data format to RGB conversion. Test module

说明：  Verilog 黄金参考指南是 Verilog 硬件描述语言及其语法 语义 合并以及将它应用到硬件设计的一个简明的快速参考指南。(Verilog Golden Reference Guide is a concise and fast reference guide for Verilog Hardware Description Language and its syntax and semantics merging and its application to hardware design.)

同步与异步FIFO的verilog实现，包括源代码，testbench，测试以及综合通过，还有相关参考资料(Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references)

异步FIFO控制器的Verilog设计与实现-Asynchronous FIFO controller Verilog Design and Implementation

二进制LDPC解码器：