done, would not have introduced the document on the bar, IEEE1364 standard (open...

mpeg-2 crcr32计算的代码，采用verilog编写，验证通过(mpeg-2 crcr32 caculate)

offset_cancellation code for matlab to hdl

在nios系统开发中的驱动i2c音频电路的代码,包括verilog代码,与相应的驱动代码(In the nios system development in the driver i2c code for the audio circuitry, including the verilog code, and the corresponding driver code)

包括很多格式的85基准电路，不需手动转换，可以供学者自行选用。(This resource including many formats 85 banchmack circuit, without manual conversion, you can choose for the scholar.)

This tutorial introduce VHDL code for clock pulse and 4-bit counter. With four bits, the counter count from 0 to 15. The timing of the counter is controlled by a clock signal. There will be a clear signal which can reset the counter value.

中央空调的控制，3级控制系统，这个是中间控制的vhdl源代码-Central air-conditioning control, 3 control system, this is the middle of the control of vhdl source code

艾米电子的verilog HDL描述的DS18B20的程序(Amy verilog HDL description of the procedures DS18B20)

FPGA简:讲述了FPGA的基本概念、结构、发展-Jane FPGA: FPGA describes the basic concepts, structure, development

RISC-V 芯片设计规范,很有参考价值，开源芯片设计必备参考资料，希望对大家有帮助。(The RISC-V Foundation is chartered to standardize and promote the open RISC-V instruction set architecture)

Turbo码编解码的FPGA实现，verilog语言编写(Implementation ofTurbo code on FPGA , using Verilog language)