done, would not have introduced the document on the bar, IEEE1364 standard (open...

UART自适应波特率发生器，其中是以文档的形式来介绍怎样实现UART波特率发生器的实现(Adaptive UART baud rate generator, which is in the form of a document to describe how to achieve the realization of UART baud rate generator)

应用背景此应用程序是用Xilinx ISE 12.4，使用VHDL语言进行。本程序的目的是提供一个显示的接口方法的七段显示。用户将可以看到从0到9999的一个计数器，它运行在利用FPGA内部的时钟实时。享受它。关键技术现场可编程门阵列（FPGA）是半导体器件是基于一个可配置逻辑块（CLB）连接矩阵通过可编程互连。FPGA可编程所需的应用或功能要求后制造。这功能区分FPGA从特定应用集成电路（ASIC），这是制造的特定设计定制任务。虽然一次性可编程（OTP）FPGA，这主要类型是基于SRAM的可重新编程的设计演变。

一个verilog语言开发编写的简单的ddr3模型(A simple model ddr3, written with verilog language)

用于单片机的adc采集实验，经过降噪处理，结果精确(ADC acquisition experiment for single chip computer, after noise reduction processing, the result is accurate)

Program to implement convolution through VHDL-Program to implement convolution through VHDL...

An FSM using VHDL and Johnson state encoding for states

SDRAM的驱动程序，主要是对SDRAM各类状态进行驱动，有刷新模块、读、写模块等。(The driver of SDRAM mainly drives various states of SDRAM, including refresh module, read and write module.)

硬件描述语言Verilog-Verilog hardware description language

蜂鸣器音乐演奏，有ppt说明，及实例工程文件。(Music buzzer, a ppt notes, and examples of engineering documents.)

这是“状态机设计（讲稿）”，希望对正在学VHDL的同学有帮助，谢谢！-This is the "state machine design (the script)", and I hope to learn VHDL is there to help the students, thank you!