康塔多0至999的VHDL接口7段显示

基于EDA技术的数字密码锁源程序代码,大学实训用的着-EDA-based Digital code lock source code, used by the University Training

matlab 程序 伪随机码的捕获,我传的都是这方面的资料！(failed to translate)

说明：  AD6 中进行FPGA设计与仿真，很不错的资料哦(FPGA design and Simulation in AD6, very good data)

说明：  asssembly ccode to turn on 7 segmen

DDS_AD9854_for FPGA ,FPGA开发下的verilog源代码，信号发生器(DDS_AD9854_for FPGA, verilog source code, signal generator.)

说明：  这是一个带声音的弹球小游戏，通过VGA口显示，通过扩展口JA的 pin4和 pin GND输出声音， BTN3 BTN2 控制挡板左右移动，弹球和挡板都自带动画效果(This is a band sound pinball game, through the VGA port shows that through the expansion of the mouth of the JA and pin4 output pin GND voice, BTN3 BTN2 control baffle around Mobile, pinball and baffle all bring their own animation effects)

VHDL学习手册-VHDL study manual

说明：  FPGA Verilog控制FLASH片外读写(Verilog Controls FLASH Out-of-Chip Read-Write)

CPLD下载线制作，内含电路图等，希望对大家有帮助-CPLD download line production, including circuit diagrams, etc., in the hope that we have to help

针对32位MIPS微处理器中CLZ指令（对单个字高位连零进行计数）的实现电路，使用了类似于超前进位的逻辑结构。包含测试文档，以及Design Compile所用的环境和脚本。(The CLZ instruction counts the number of leading zeros in a word. The 32-bit word in the GPR rs is scanned from most-significant to least-significant bit.The number of leading zeros is counted and the result is written to the GPR rd. If all 32 bits are cleared in the GPR rs, the result written to the GPR rd is 32. )