康塔多0至999的VHDL接口7段显示

基于sopc的lcd时钟，开发工具为nios ii和quartus ii9.0(Based on sopc the lcd clock, development tools for the nios ii and quartus ii9.0)

4weimimasuo 可运行 可仿真 -aetgdffh tghj tjfgj fdg vbn t

VHDL语言实现PWM信号，非常方便的使用-VHDL language realize PWM signal, very convenient to use

说明：  并行读写14路串口数据，数据被写入FIFO，在收到读写信号后，SPI发送数据出去(Parallel read and write 14 serial port data, SPI send data)

说明：  Quartus II TimeQuest 时序分析器说明书；这本手册包含一组设计场景、约束指南以及相关建议。您应该熟悉 TimeQuest Timing Analyzer 和 Synopsys Design Constraint(SDC) 的基础知识，以便正确地使用这些指南。(Quartus II timequest timing analyzer manual; this manual contains a set of design scenarios, constraint guidelines, and related recommendations. You should be familiar with the basics of timequest timing analyzer and Synopsys design constraint (SDC) to use these guidelines correctly.)

集成电路的规模日益扩大

说明：  FPGA 读写 SRAM 存储块，verilog代码(Read and write SRAM memory block and Verilog code in FPGA)

Actel FPGA A3P600最小系统原理图，包含JTAG 、电源和封装 (Actel FPGA A3P600 minimum system schematics, including JTAG, power and packaging)

基于Verilog的小波滤波器程序设计的总结文档。(Verilog based wavelet filter program design summary document.)

yuv444 与yuv422相互转换verilog语言(yuv444 to yuv422)