串并转换程序，由串行输出转换为4位的并行输出

基于FPGA的图像压缩算法程序，自己写的，可以参考一下(FPGA-based image compression algorithm, write your own, you can refer to)

AB相编码器解码接口_PWM输出SOPC方案及其在运动控制卡和伺服驱动器中的应用(AB phase encoder decoder interface _PWM output SOPC program and its application in motion control card and servo drive)

通过FPGA驱动千兆以太网口，完成SPARTAN6上的UDP数据包闭环测试，即通过网口发送数据包到FPGA，FPGA内部将接收到的数据返回到PC机，建议测试之前添加ARP静态绑定，FGPA内部的IP以及MAC地址在ROM里的COE文档里可以看到，发送端添加了CRC以及整体CHECKSUM的计算(Driven by FPGA Gigabit Ethernet port, UDP SPARTAN6 data packet on the closed loop test, through the network to send data packets to FPGA, FPGA will receive the data back to the PC, the proposed test before adding ARP static binding, FGPA internal IP and MAC address in the COE document in the ROM where you can see, the sender adds CRC and CHECKSUM integral calculation)

fpga clock 设计，资料较好，供大家参考，非商用目的哦-fpga clock design, the information is better, for your reference, non-commercial purposes Oh

class diagram diagram for AIRS

说明：  用于生成adams或recurdyn所需的路面不平度，用于悬架或其他的仿真(Adams or recurdyn used to generate the required road roughness for suspension or other simulation)

基于FPGA的pci总线接口设计。。。。。。。。。。。。。(FPGA-based PCI bus interface design)

5对于进入密码锁的钥匙，假设复位后七节灯显示为" 0"，而使用sw1、sw2两个，则sw2-> sw1-> sw1-> sw2，则表示解锁右侧将导致七节灯显示为" 8"

A programming language that can decode alpha numeric

VHDL实现的8位乘法器，所有仿真全部通过-VHDL to achieve 8-bit multiplier