串并转换程序，由串行输出转换为4位的并行输出

实现了简单的电子表功能，是24小时，用VHDL所编写的，quartus ii 7.2-To achieve a simple spreadsheet functions, is 24 hours, using VHDL prepared, quartus ii 7.2

说明：  there's a clock divider for DE2 altra board clock (50MHz)

用verilog语言实现加密芯片DS28E01的调用操作命令。(Using Verilog language to achieve the encryption chip DS28E01 call operation commands.)

verilog写的39阶通带为20KHz的半带fir滤波器，经测试正确。(verilog halfband FIR)

上/下计数器是有用的大规模集成

说明：  basys3的数字钟，可以显示00.00-59.59(Digital clock of basys3,It can display 00.00-59.59)

Xilinx user constraints file for the cpld xc9536 or xc9536xl or xc9572 or xc9572xl

freeDev数字应用开发板中的VGA控制器的IP核的verilog实现-freeDev digital application development board of the VGA controller IP core implementation of the verilog

一个简单的用verilog实现的售货机状态机设计，内有word介绍设计的原理(A simple realization of a vending machine with verilog state machine design, there are design principles introduced word)

interruption routine for PIC16F877