VHDL常用源程序，希望以EDA技术学习者有用！

一个8X8的矩阵键盘的VHDL文件,并且有长安键和短按键之分,即一共能做到128个键值,扫描用的时钟用1ms的就行了-A 8x8 matrix keyboard VHDL files and have Changan and short keys of key points, namely, to achieve a total of 128 keys, scanning with the clock used on the list of 1ms

基于FPGA的17阶FIR滤波器VHDL代码及说明文档-fpga fir

基于FPGA器件的DDS设计实现中的一个核心部分就是波形存储表的设计。首先采用LPM_ROM和 VHDL选择语句这两种方法进行波形存储表的设计和比较分析 然后考虑到硬件资源的有限性及DDS的精度要 求,对这两种方法的程序进行了优化 最后对这两种方法设计的程序进行仿真和硬件调试。结果表明:采用这两种 方法都能有效地实现DDS中波形存储表的设计。 (DDS-based FPGA devices designed to achieve one of the core of the waveform is stored in table design. First of all, choose to adopt LPM_ROM and VHDL statements of these two methods for the design waveform storage tables and comparative analysis and then, taking into account the limited hardware resources and the accuracy of DDS, the two methods to optimize the process the last of these two methods of process design simulation and hardware debugging. The results showed that: the use of these two methods are all effective ways to achieve the DDS waveform stored in the table design.)

SDRAM的vegilog代码，做一个SDRAM的封装成为SRAM一样进行操作。一个顶层文件下由三个模块-SDRAM

This an interpolating by 2 half-band filter with 79 taps (40 none-zero coefficients).

verilog 简易频率计的设置，包括整个工程(verilog simple frequency meter settings, including the entire project)

本例程位于 VMD642_CPLD目录中。 使用 CPLD 实现辅助译码、LED 指示灯控制、看门狗等各种逻辑控制电路。源程序使 用 Verilog HDL书写，编译开发系统使用 Cypress公司的 Warp 6.3。(This routine is located VMD642_CPLD directory. Using CPLD implementation auxiliary decoding, LED indicator control, watchdog, and other logic control circuitry. Written using Verilog HDL source code, the compiler development system using Cypress' s Warp 6.3.)

流水线乘法器的VHDL实现，希望对你会有用！-Pipelined multiplier in VHDL implementation, you will want to use!

LOW pass FIR filter for multirate processing

基本的usb驱动程序的编程方法,值得一看.-Basic programing method for USB driver, worth reading