very much verilog code for the beginner

VHDL实现快速傅立叶变换 -VHDL implementation VHDL implementation of Fast Fourier Transform Fast Fourier Transform

采用DDS方法在FPGA上实现频率发生器，最大频率设置在9999Hz，输出正弦波。 DDS是一种从相位概念出发直接合成所需要的波形的新的全数字频率合成技术。同传统的频率合成技术相比，DDS技术具有极高的频率分辨率、极快的变频速度，变频相位连续、相位噪声低，易于功能扩展和全数字化便于集成，容易实现对输出信号的多种调制等优点，满足了现代电子系统的许多要求，因此得到了迅速的发展。

本人上网下载下来并调试过的，完全实现NIOS 下对SD卡读写及包括FAT16文件系统的实现，使用的是QT8.1，FPGA里实现，里面有详细接线图，是完整的一个工程，在EP2C20Q240C8里调试成功-I downloaded off the Internet and debug off, and the full realization of NIOS under the SD card reader and includes FAT16 file system implementation, using QT8.1, FPGA years to achieve, which detailed wiring diagram, is a complete one project in EP2C20Q240C8 debug in the success of

通过数码管和单片机的组合 制作成的数码管时钟程序(Through the combination of digital control and made ​ ​ into a single-chip digital clock program)

CAN总线的数据采集，FPGA到USB。verilog hdl语言。(CAN bus data acquisition, FPGA to the USB. verilog hdl language.)

vhdl code for fir filter

PS2 Module for Altera DE2

BT656 时序, 逐行, 分辨率1280*960@25Hz(BT656 time series, row by row, resolution 1280*960@25Hz)

verilog 编写的I2C程序，控制D/A的(I2C program written by Verilog to control D/A)

This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.