very much verilog code for the beginner

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VERILOG实现无分频时钟，包括测试文件，经过验证可用(VERILOG is no difference between the frequency of the clock implementation, including test papers, can be used after authentication)

用于FPGA的学习，大家值得借鉴，可以好好学习一下(this is for fpga and you can use this.)

存储器控制FPGA程序，包括ram，fifo，sdram，flash等。-FPGA memory control processes, including ram, fifo, sdram, flash and so on.

鉴于stm32在keil平台上的ADC采集转化，在LCD屏上显示程序(voltage acquisition adc)

Verilog HDL编写的键盘扫描程序，考虑了判断按键弹起的问题。程序按一定的频率用低电平循环扫描行线，同时检测列线的状态，一旦判断有一列为低则表示有键被按下，停止扫描并保持当前行线的状态，再读取列线的状态从而得到当前按键的键码；等待按键弹起：检测到各列线都变成高点平后，重新开始扫描过程，等待下一次按键。-Written in Verilog HDL keyboard scanner, taking into account to determine key bounce problem. Program according to a certain frequency of scan lines with low-level circulation lines, while testing out the state line, once the judge has said there is a classified as low-key is pressed, stop the scan and to maintain the current line-line state, and then read out line state to get the current keys key codes to wait for key pop-up: To detect the lines at all out into a high level after the re-start the scanning process, waiting for the next key.

FIR filter up to 128x

Traffic light program in c presents what happens in our daily life at traffic light signals.

它工作斯巴达。 使用 xilinx ise 在斯巴达 6e 效果很好

this is a sum for 2 digit numbers