USB口的设计，包括驱动程序的设计，以及软件的安装演示，软件的介绍，以及工作模式...

reversible Data Hiding in Encrypted Images by Reserving Room Before Encryption

跑马灯 简单实用很适合初学者 希望对大家有用-Marquee is simple and practical very suitable for beginners want to be useful to everyone

按键可调占空比的PWM波产生程序。语言：VHDL(Button adjustable duty cycle of the PWM wave generator. Language: VHDL)

Oregano Systems 8051 ip核-Oregano Systems 8051 ip core

适用于FPGA的SOPC方面的元器件添加，如COMPNENT-Applicable to FPGA-SOPC area to add components, such as COMPNENT

its a verilog code for microcoded tb

vhdl testbentch 编写模板。非常实用-vhdl testbentch prepared templates. Useful

8位十六进制频率计设计 根据频率的定义和频率测量的基本原理，测定信号的频率必须有一个脉宽为1s的输入信号脉冲计数允许信号；1s计数结束后，计数值被锁入锁存器，计数器清零，为下一测频计数周期做好准备。测频控制信号可由一个独立的发生器（FTCTRL）来产生。-8-bit hexadecimal Cymometer designed in accordance with the definition of frequency and frequency of the basic principles of measurement to determine the frequency of the signal must have a pulse width of the input signal for 1s permit pulse counting signal 1s counting after the total value was locked into the lock depositors, counters cleared for the next count cycle frequency measurement ready. Frequency control signal generator may be an independent (FTCTRL) to generate.

高速DDR存储器数据接口设计实例. 1. 将文件拷入硬盘 2. 产生DQS模块 3. 产生DQ模块 4. 产生PLL模块 5. 拷贝以上步骤生成的文件到子目录【Project】中 6. 打开子目录【Project】中的DataPath.qpf工程，设计顶层模块 7. 编译并查看编译结果 (High-speed DDR memory interface design data. 1. Copyed into the document hard disk 2. DQS generated module 3. Have a DQ module 4. Have a PLL module 5. Copies of the above steps to generate a document to a subdirectory 【Project】 6. Open the subdirectory 【Project】 DataPath.qpf in engineering, design top-level module 7. compilers to compile the results and see)

说明：  通过spi实现加速度计adxl357读取xyz三轴方向的加速度值(Accelerometers adxl357 read the acceleration value of XYZ three-axis direction through SPI)