lgpl RS编解码 5

用verilog语言写的简单的键盘扫描代码，适合初学者，用alter的软件编写的程序代码。(Using verilog language to write simple keyboard scan code, suitable for beginners, with alter software program written code.)

用verilog编写的分辨率提高的源代码 采用双线性插值(Written resolution with the verilog source code to improve the use of bilinear interpolation)

ModelSim的使用如何操作和使用以及安装如何安装

一个用VerilogHDL语言编写的多路解复用器-a Verilog HDL language used in the preparation of multi-channel demultiplexer

VHDL cyclic redundancy check generator und receiver

verilog实现的“六进制约翰逊计数器”。(verilog implementation of the " six hexadecimal Johnson counters." )

design and implementation of a format conversion system on the Altera NIOS board(QUARTUS) which reads an analogue input, converts it into digital data, and then does the reverse conversion back into analogue format. This will be done by taking an analogue an analogue input using SPI MCP3202 12-Bit A/D converter to generate the digital data stream and then the digital data will be used to generate an analogue output using Analog Devices 8-bit SPI AD7303 D/A converter.

this a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the supporting file for keyboard interface and it also included a intro.vhdl file required for the startup animation file.-this is a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the supporting file for keyboard interface and it also included a intro.vhdl file required for the startup animation file.

使用VHDL编程的异步FIFO程序 经调试可运行-Using VHDL programming asynchronous FIFO procedure can be run by the debugger