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DDR3读写测试

于 2018-03-28 发布 文件大小:780KB
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  MIG IP控制DDR3读写测试,于MIG IP核用户接口时序较复杂,这里给出扩展接口模块用于进一步简化接口时序。(MIG IP controls DDR3 reading and writing tests, and the time sequence of MIG IP kernel user interface is more complex.)

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DDR3读写测试.docx, 861701 , 2018-03-28

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