8位CPU的VHDL设计代码没有测试

说明：  matlab代码，利用Farrow结构设计分数延时滤波器，滤波器阶数和个数可分别进行设置，利用最大最小准则近似。(Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.)

说明：  第1例到第6例的源描述都是从第8例的程序包中 提取出来的,不能单独编译,这些例子的编译与 模拟请参考第8例.(Example No. 1 to the first six cases are the source described in Example 8 from the first package to extract it and can not be a separate compiler, which compiler and simulation examples please refer to the first eight cases.)

ADS7844 AD转换芯片的VHDL控制器-ADS7844 AD converter chip VHDL controller

verilog code,about oc8051

可以产生8比特的采样波形，非常不错的VHDL程序(Sampling can produce 8-bit waveform, very good VHDL program)

Module for filtering input digital signal

cordic算法的verilog 语言实现，注释详细，资料齐全，实现了cordic算法的各个功能，可以计算正余弦(cordic algorithm verilog language, detailed notes, and complete information)

提供了100个vhdl硬件编程语言的例子,由简单到复杂-100 provides a hardware programming language VHDL examples, from simple to complex

该程序是一个可完成订制化的SPI双向总线接口，时钟相位、极性，以及分频比全部可通过寄存器进行配置，已经在ISE下通过综合，占用资源少，强烈推荐 (The program is a complete custom of SPI bidirectional bus interface, clock phase, polarity, and the divider ratio can all be configured through the register, has been in the ISE through an integrated, small footprint, it is strongly recommended)

this program is a simulation for Aloha