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SHIFT_8REG是8位的一个具有移位功能的寄存器,每一次数据打入都会从这个寄存器的最低位打入,并相应进行向左移位。
ODD_110BREG是一个3位的备...
SHIFT_8REG是8位的一个具有移位功能的寄存器,每一次数据打入都会从这个寄存器的最低位打入,并相应进行向左移位。
ODD_110BREG是一个3位的备份寄存器,寄存器中存放的是奇数帧的同步头,也就是110。
EVEN_9BHREG是一个8位的备份寄存器,寄存器中存放的是偶数帧的同步头,也就是10011011。这两个寄存器的初始值在系统一开始就打入。
-SHIFT_8REG is eight with a displacement of the functional Register, Each will enter the data from the register into the lowest point, and the left shift accordingly. ODD_110BREG is a three backup Register, the Register is stored in the odd frame synchronization head, is 110. EVEN_9BHREG 8 is a backup Register, which register is kept even the first frame synchronization, is 10011011. This register the two initial value of the system into a start.
- 2022-05-15 03:11:22下载
- 积分:1
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sm4_Verilog
sm4 VERILOG 代码实现及其在无线网络3G中的应用(sm4 VERILOG)
- 2020-08-11 20:58:27下载
- 积分:1
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FFT
FFT with fix point 2*N
- 2013-10-06 15:38:38下载
- 积分:1
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本代码介绍了使用VHDL开发FPGA的一般流程,最终采用了一种基于FPGA的数字频率的实现方法。该设计采用硬件描述语言VHDL,在软件开发平台ISE上完成,可以...
本代码介绍了使用VHDL开发FPGA的一般流程,最终采用了一种基于FPGA的数字频率的实现方法。该设计采用硬件描述语言VHDL,在软件开发平台ISE上完成,可以在较高速时钟频率(100MHz)下正常工作。该设计的频率计能准确的测量频率在1Hz到100MHz之间的信号。使用ModelSim仿真软件对VHDL程序做了仿真,并完成了综合布局布线,最终下载到芯片Spartan-II上取得良好测试效果。-the code on the FPGA using VHDL development of the general process, finally adopted a FPGA-based digital frequency method. The design using VHDL hardware description language, the software development platform ISE completed, the higher speed clock frequency (100MHz) under normal work. The design of the frequency meter can be accurately measured in a frequency of 100MHz between Hz signal. Use ModelSim VHDL simulation software to do the simulation process, and completed a comprehensive layout cabling, downloaded to the final chip Spartan-II made good on the test results.
- 2022-10-09 05:15:03下载
- 积分:1
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用FPGA实现数字锁相环,开发环境为ISE
用FPGA实现数字锁相环,开发环境为ISE-Using FPGA digital phase-locked loop, development environment for ISE
- 2022-06-22 05:34:34下载
- 积分:1
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61EDA_C2212
红色飓风II开发板USB2FPGA USB驱动程序,由verilog编写,包括源码和FIFO测试程序(Red Hurricane II development board USB2FPGA USB driver from verilog preparation, including source code and test procedures FIFO)
- 2013-05-30 14:22:07下载
- 积分:1
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Verilog语言手册
Verilog Language Manual
- 2022-04-19 20:28:43下载
- 积分:1
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RS485
verilog开发FPGA,实现RS485串口通信(RS485 driver for FPGA )
- 2021-02-08 06:49:54下载
- 积分:1
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Digital stopwatch in the stopwatch with start, reset, suspend, suspended after t...
数字跑表
该跑表具有启动、复位、暂停、暂停后继续计时等功能
能显示的秒计数时间精确到小数点后第二位,即能显示**.**s
按钮设置防抖-Digital stopwatch in the stopwatch with start, reset, suspend, suspended after the time and other functions can show the seconds counting time accurate to the second place after the decimal point, that can show**.** s Anti-Shake button settings
- 2022-01-21 20:07:05下载
- 积分:1
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program vending machine at the core function, with three kinds of commodity pric...
程序实现自动售货机的核心功能,设有3种价格的商品,可选择数量,有找钱功能。-program vending machine at the core function, with three kinds of commodity prices, the number of choice, having to function.
- 2022-12-29 09:45:03下载
- 积分:1