实用的程序代码，希望对大家有用，已经调试通过

说明：  ADDER USING VERILOG ADDER WITH VERILOG VERILOG ADDER

适用于NIOS II的1024点FFT C算法( 1024-point FFT C algorithm for NIOS II)

使用synopsys的基本步骤，综合工具的使用说明，有用的好东西-Synopsys using the basic steps to use the integrated tools, useful good things

wavelet transform of a signal,it is important and useful code to trans form frequency to time domain

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is licensed under MIT License

this is an peak detection alguritm,in this matlab code u can clean base line noise to have clear ECG signal

Frame Control field
Retry:
Set in case of retransmission frame
More fragments:
Set when frame is followed by other fragment
Power Management
bit set when station go Power Save mode (PS)
More Data:
When set means that AP have more buffered data for a station in Power Save mode

Verilog代码，支持IO，中断的cpu实现。(Verilog code, support IO, interrupt cpu implementation.)

基于fpga状态机的交通灯设计，亮灯时间自己修改，程序简单易懂。(Traffic light design based on FPGA state machine, light time self-modifying, the program is simple and easy to understand.)

用32位NiosII处理器实现RS232通信，可以给初学者一个借鉴。-NiosII with 32-bit processors to achieve RS232 communication, can give a reference for beginners.