用Verilog HDL语言编写的AT24C04程序，并用数码管显示，已经过测试，很好用...

超低速的光纤一体发接收发送器,同于以前的光纤一体化接头都只适用于2M以上的通讯,如需将232等低速信号用光纤传输出,需要加复杂的调制解调电路,网动光电新生产的这款光纤头主要针对低速信号,可以传送DC-500KPS的信号,极大地简化了硬件设计.(Ultra-low-fat whole-speed fiber-optic transmitter receiver with fiber-optic integration in the previous joint only applies to more than 2M communications, etc. For the 232 low-speed optical fiber transmission of signals, the need to increase the complexity of the modulation and demodulation circuit, the net move Photoelectric new production of this first major response to low-speed fiber-optic signal, DC-500KPS can send the signal, greatly simplifying the hardware design.)

DDR SDRAM控制器verilog代码及中文说明文档,对DDR开发很有用的哈。-Verilog source code for DDR SDRAM controler design,including guide book in chinese.

介绍了如何用vhdl语言实现处理器的spi接口-Describes how to use VHDL language processor spi interface

摘 要：以上海地区的出租车计费器为例，利用Verilog HDL语言设计了出租车计费器，使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优 化，下载到EPF1OK10TC144—3芯片中，可应用于实际的出租车收费系统。 关键词：Verilog HDL；电子自动化设计；硬件描述语言；MAX+PLUSⅡ(Abstract: Shanghai taxi meter as an example, the use of Verilog HDL language designed taxi meter so that it will have the time display, billing, as well as analog taxis to start, stop, reset and other functions, and set up a dynamic scanning circuit shows that the fare and the corresponding time, shows the hardware description language Verilog-HDL design of the superiority of digital logic circuits. Source by MAX+ PLUS Ⅱ software debugging, optimization, downloaded to EPF1OK10TC144-3 chip, can be applied to the actual taxi fare collection system. Keywords: Verilog HDL electronic design automation hardware description language MAX+ PLUS Ⅱ)

VHDL的初学者可以参考此VHDL加法器，相信会给你带来不小的收获-VHDL beginner can refer to the VHDL adder, I believe will bring you not a small harvest

这是我自己写的4位并转串ISE代码，在xilinx Spartan3E 上已经调试成功，拿出来与大家分享！-that I wrote four string and turn ISE code In xilinx Spartan3E debugging has been successful, with the show to share with you!

完成GPS的IRIG_B码解码，已经模块化，并且有详细的中文注释(Completed the GPS IRIG_B of decoding modular, and there are detailed notes in Chinese)

vhdl um teste com muita coisa interessante ae pra ver

4 bit ROM for Quartus

华为内部的FPGA设计培训教程，详细阐述了设计流程图、Verilog HDL设计、逻辑仿真、逻辑综合。对大家的学习一定有帮助的。-Huawei within the FPGA design training tutorial, a detailed flow chart of the design, Verilog HDL design, logic simulation, logic synthesis. Study of the U.S. must have help.