用Verilog HDL语言编写的AT24C04程序，并用数码管显示，已经过测试，很好用...

evga-indtube.h - Keytable for evga_indtube Remote Controller.

可以直接用于工程应用的crc校验VHDL编码 里面有详细的规格书-Can be directly used for engineering applications of CRC checksum inside VHDL code has detailed specifications

24,60,100进制的计数器，还有数字时钟，欢迎下载哦~-24,60,100 229 of the counter, digital clock also welcome to download oh ~

用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core.-algorithm using the symbols multiplier, HDL-piece quantities. it is not necessary for the company"s paid Multiplier ip core.

Demo program for use UART STM8S

FPGA对系统50M时钟进行分频。FPGA最基本功能基础(FPGA Verilog program, key detection, program jitter elimination, jitter elimination, delay detection keys)

64点FFT代码 基4算法 Verilog(64-point FFT code radix-4 algorithm Verilog)

FPGA控制AG9226进行采样的代码,并用signaltap测试了一下其正确性(FPGA control AG9226 to sample the code, and use signaltap to test the correctness of the demo.)

FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation