用Verilog HDL语言编写的AT24C04程序，并用数码管显示，已经过测试，很好用...

REEDSOLOMON source code

VHDL USB2.0接口源码,内有说明,详细.-VHDL USB2.0 interface source code, which is described in detail.

设计一简易数字频率计，其基本要求是： 1)测量频率范围0～999999Hz； 2)最大读数999999HZ,闸门信号的采样时间为1s；. 3)被测信号可以是正弦波、三角波和方波； 4)显示方式为6位十进制数显示； 5）具有超过量程报警功能。 5)输入信号最大幅值可扩展。 6）测量误差小于+-0.1%。 7)完成全部设计后，可使用EWB进行仿真，检测试验设计电路的正确性。(The basic requirements of designing a simple digital frequency meter are: 1) The measuring frequency range is 0-999999 Hz. 2) The maximum reading is 999999HZ, and the sampling time of gate signal is 1 s. 3) The measured signal can be sine wave, triangle wave and square wave. 4) The display mode is 6-bit decimal number display. 5) It has alarm function beyond range. 5) The maximum amplitude of input signal can be expanded. 6) The measurement error is less than +0.1%. 7) After completing all the design, EWB can be used to simulate and test the correctness of the circuit.)

一个实用的uart协议模块，使用verilog 实现(A practical uart protocol modules, use verilog to achieve)

VHDL 波形防止抖动程序,学习试验材料(VHDL prevent jitter waveform procedures, the pilot study materials)

用verilog语言实现加密芯片DS28E01的调用操作命令。(Using Verilog language to achieve the encryption chip DS28E01 call operation commands.)

vhdl实现vga接口设计，非常实用的一段代码，学习用-vhdl achieve vga interface design

用FPGA分频，做一个有时分秒的时钟，并用数码管显示(FPGA divide a sometimes every minute clock, and digital display)

VHDL语言实现PWM信号，非常方便的使用-VHDL language realize PWM signal, very convenient to use

用汇编语言设计的频率计，注释较详细，适于初学者学习使用(Assembly language design frequency meter, the comment in more detail, suitable for beginners to learn to use)