ADC VHDL 代码

encoder using else if statement

rc6 algorithm designed based on verilog and is verified

说明：  使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。(The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.)

里面含有vhdl和verilog 版本,很好用!dct变换用得很多啊!(Which contains a VHDL and Verilog versions of very good use! Dct transform with a lot ah!)

基于Verilog的小波滤波器程序设计的总结文档。(Verilog based wavelet filter program design summary document.)

用VHDL实现了希尔伯特滤波器,即就是幅度不变，而相位移动90度(use vhdl to accomplish the hilbert filter)

说明：  displayport 参考设计，可以对比自己工程做验证，另有参考设计XAPP1178未找到，采用方案为DP159 + Artix7 FPGA(xilinx displayport sink design)

出租车vhdl程序，并带有testbench仿真程序，通过开始按键复位，然后根据行使信号进行公里计数，起步价3公里8元钱，超过3公里一公里1元钱(Taxi vhdl program, with a testbench simulation program, started by the reset button, then the exercise kilometer count signal, starting at 3 km 8 yuan, more than three kilometers one kilometer dollar.)

一篇关于FIFO设计以及FPGA设计的文章-FIFO 1 on the design and FPGA design article

《Verilog HDL 程序设计教程》6-"Verilog HDL Design Guide" 6