介绍了光纤光栅感温火灾探测系统的应用原 理，并重点阐述了用CPLD 设计虚拟MC14499 器件模 块，给出并解释了用Verilog HDL 语言实现的...

FPGA UART 发送端程序 verilog语言编写 9600波特率 实用(UART transmit side program verilog language 9600 baud)

Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.

verilog 语言实例，对于新手学习有很大帮助的实例-Examples of Verilog language, the novice has to learn very helpful examples of

FIR滤波器的verilog HDL代码示例，以16阶为例(Verilog HDL code for fir filter)

状态机的典型饮用，可供学习模仿之用，四个状态，简单易学(State machine of the typical drinking, can be used to learn to imitate, four state, easy to learn)

一个FIFO产生程序，主要是一个格雷码的加法器(A FIFO generation process, is primarily a gray code adder)

非常好的verilog书 国际牛人写的 适合各个阶段学习的人(Very good Verilog books were written in the international cattle suitable for the various stages of learning)

说明：  access must be conf urr arr

SPH的原始代码，希望可以帮到大家啊关于模拟poiseuille的(simulate poiseuille fuild)

说明：  FPGA控制AD7656和模拟开关实现36路模拟量循环采集(FPGA control AD7656 and analog switch to realize 36 channels of analog cyclic acquisition)