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VHDL语言编程简单实例若干，适合于初学者(VHDL language programming simple example, suitable for beginners)

4X4 KEYPAD 的输入位数计数器，可以自己定义输入的位数-4x4 KEYPAD median counter input, input their own definition of the median

VHDL Programing

说明：  用VHDL语言实现电子钟(Using VHDL language electronic bell)

ad9361 matlab驱动代码，运行此代码可在matlab中控制AD9361(AD9361 matlab driver code, running this code can control AD9361 in MATLAB)

本设计是基于FPGA的一个FIR低通滤波器设计，要求使用Verilog语言编写滤波器模块，通过编译和综合，并通过Matlab和modelsim联合仿真验证设计结果。(This design is a FIR low-pass filter design based on FPGA, use Verilog to program filter module, and joint simulation by Matlab and modelsim to validate the design results.)

FPGA实现DSP的Verilog 示例(FPGA realization of DSP-Verilog Example)

TD-LTE中（3.1.7）咬尾卷积码编码器verilog代码(Tail-biting convolutional code encoder verilog code)

说明：  FPGA的fifo与dsp的emif接口测试程序(EMIF interface test program for FIFO and DSP of FPGA)

一个在CPLD，EPM70128上实现的PWM控制源程序。(A CPLD, EPM70128 realize the PWM control on the source.)