SPI的verilog代码的可编程时钟

实现十六位加法器，是书籍上配套的应该可用-This is an 16 bit adder using vhdl

实现FPGA与PC通信的USB2.0接口,采用verilog语言实现(Implementation of FPGA and PC communication USB2.0 interface, using Verilog language to achieve)

DESCRIPTION OF FULL ADDER

HDB3的VHDL语言描述，注释在文件内(HDB3 source code in VHDL)

基于DVI协议动态全彩LED大屏幕发送卡设计与实现,成本比较低,效果很好,可以实现高清视频(Dynamic full-color LED large screen based on the DVI protocol send a card design and relatively low cost, good effect, and can achieve high-definition video)

一个完整的viterbi编码程序，使用vhdl语言编写，还有测试程序-A complete viterbi coding procedures, the use of VHDL language, as well as test procedures

这是我准备电子设计大赛时，用VHDL写的一个自动打铃系统，很好的学习资料。-This is when I am going to Electronic Design Contest, use VHDL to write an automatic bell playing system, a very good learning materials.

汉明码转换，在FPGA上用verilog实现(hamming encoder, using FPGA)

介绍了基于VHDL的可编程分频器在波形发生器中的应用的方法，利用这一方法， 可使波形频率在大范围内变化。()

10进制计数器，VHDL描述的，实验必备-10 hexadecimal counters, VHDL description of the experiment must