SPI的verilog代码的可编程时钟

AD9268的配置Verilog实现，程序用于实现4通道的AD9268的配置(The 4 channel AD9268 configuration)

c54x的VeriLog程序代码 也是opencoreip-C54x is the Verilog code opencoreip

verilog编写的alu模块-Verilog modules prepared by the ALU

基于Montgoery 算法的RSA,FPGA verilog 实现，有测试文件(Based on Montgoery algorithm for RSA,FPGA verilog implementation，bench file)

VHDL上机手册（基于Xilinx ISE） ___________________________________________________ 1 ISE 软件的运行 2 创建一个新工程 3 创建一个VHDL源文件框架 4 输入VHDL程序 *5 仿真 6 创建Testbench波形源文件 7 设置输入仿真波形 -eda

在FPGA内使用PID算法反馈控制小车速度和方向，四电机独立(PID algorithm within the FPGA using feedback control the car speed and direction, four independent motors)

说明：  C8051F的一个特点就是可以倍频到100M。近来用到。在单片机的调试通过其PLL倍频函数。供用到的朋友参考和借鉴。(One feature is the ability C8051F multiplier to 100M. Recently used. In MCU debugging functions through its PLL multiplier. Used for reference for a friend.)

可编程逻辑器件cpld与单片机双向通信的源程序-Programmable logic device CPLD and MCU for two-way communication of the source

VHDL语言按VGA接口标准把数字图像信号转换成标准VGA格式。适合做学习试验-VHDL by VGA interface standards, digital image signal conversion into a standard VGA format. Suitable for the pilot study

FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation