用VHDL实现视频控制程序,实现对图像的采集和压缩,

VHDL Design of BCD to 7-segment decoder using PROM

一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了在Xilinx公司的ml505 FPGA上的位码文件和配置文件，可以直接下载使用！-A VHDL design with the use of powerful 32-bit CPU, this file contains the Xilinx company on the ml505 FPGA code and configuration files, you can direct download!

说明：  模拟交通灯 verilog CPLD EPM1270 源代码(Simulation of traffic lights verilog CPLDEPM1270 source code)

基于BCD码的十进制ALU设计，可实现加减乘除的功能(BCD to decimal ALU based design can achieve the arithmetic function)

说明：  Verilog 入门,如果你要很了解Verilog你不用先谖完一本厚厚的书还弄不清楚Verilog到底在干啥事,这份资料有助於快速了斛Verilog(Verilog Basic, If you try very hard to understand verilog by read a thick book, try read this first you will get a quick understanding of verlog.)

基于fpga的物理不可克隆函数（PUF）模块的实现(A PUF Design for Secure FPGA-Based Embedded Systems)

卷积码编码译码程序以及其modelsim仿真波形文件等(Convolutional code encoding and decoding procedures and the Modelsim simulation waveform file)

按键消抖，对时钟沿计数决定是否将bin值给内部的按键值。(Debounced buttons, whether on the edge of the clock count within the bin value to the key value.)

这是我自己写的4位并转串ISE代码，在xilinx Spartan3E 上已经调试成功，拿出来与大家分享！-that I wrote four string and turn ISE code In xilinx Spartan3E debugging has been successful, with the show to share with you!

使用spi模式初始化w5100，实现了快速以太网的初步建立(Using the spi mode initialization w5100, to achieve the initial establishment of a Fast Ethernet)