用VHDL实现视频控制程序,实现对图像的采集和压缩,

ep9351芯片的一个读取寄存器的测试程序，因为他的读取方式跟别的i2c设备不同，所以重新封装了一些i2c读写的接口。(one read ep9351 chip registers testing procedures, because he read i2c device with another different way, so repackaging some i2c interface to read and write.)

ADC Reference code!Clock 100kHz

带LDN的的同步的预置数端子，并且带CLR的异步清零端-LDN synchronization with the preset number of terminals, and cleared with CLR Asynchronous client

verilog写的39阶通带为20KHz的半带fir滤波器，经测试正确。(verilog halfband FIR)

programe reverse a string in c

下采样与灰度

说明：  uart implementation and documentation, this describes the basic steps in building your own uart module on verilog and programming them on an fpga device

详细的说明了FPGA设计的整个流程 FPGA设计全流程Modelsim>>Synplify.Pro>>ISE(Detailed description of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE)

fpga paper function fff(fpga paper function)

uart16550 ip core 通用异步收发器vhdl源代码-uart16550 ip core UART VHDL source code