用VHDL语言仿真交通灯 用VHDL语言仿真交通灯

说明：  基于altera fpga的fir IP核实现希尔伯特变换，有matlab仿真(Based on Altera FPGA fir IP core to achieve Hilbert transform, matlab simulation)

48阶FIR设计，采用VHDL语言描述，门级映射……(48-oders FIR design with VHDL language and gate level)

To increase simulation speed, ModelSim® can apply a variety of optimizations to your design. These include, but are not limited to, mergingprocesses, pulling constants out of loops, clock suppression, and signal collapsing. You control the level of optimization by specifying certain switches when you invoke the compiler.

VHDL operators basics

verilog code for 8 bit alu

一个异步FIFO的verilog实现论文-err

VHDL implementation using mouse and monitor

 本程序应用VHDL硬件描述语言，以QuartusⅡ8.0为开发工具设计了一个具有自动演奏乐曲功能的系统，演奏乐曲为《梁祝》，具有单曲播放器功能。本程序简单易懂，可作为FPGA入门学习之用。

用VHDL语言实现一Mealy型时序电路，并做时序仿真和功能仿真检验正确与否。(Implement a Mealy-type sequential circuits using VHDL language, and do functional simulation and timing simulation test correct.)

This is the source code for I2C(Inter Integreted Circuit) which is used in serial communication