有关verilog的硬件实现VGA设计的代码。

基于用户自定义模块的实时时钟的设计；Qsys硬件设计；(Custom real-time clock module-based design Qsys hardware design )

使用vhdl语言编写的100个常用程序的例子-The use of VHDL language 100 examples of commonly used procedures

使用VHDL语言编程，烧录在芯片运行的倒数5秒响4声短铃最后一声长音的数字钟-The use of VHDL language programming, burn in the chip to run the last 5 seconds short bell ring 4 final say sound a long tone of digital clock

基于VHDL的I2C程序0002,很不错的论文及程序，，大家快下啊-based on the I2C procedures VHDL 0002, a very good paper and procedures, we quickly under ah

这个是用VHDL实现的正负脉宽调制器，同样是对新手有帮助，高手不必看了。-This is achieved using VHDL positive and negative pulse width modulator, the same is to help novice, you do not have to read. Ha ha

FPGA设计频率计全套资料，我希望对大家啊好似有用的-FPGA design of a full set of frequency data, I hope all of you ah like useful

说明：  verilog语言编写的dac5687的接口程序，串行模式控制。(written dac5687 verilog interface program, serial mode control.)

1、掌握WALSH码产生的原理和WALSH码的特性。 2、掌握WALSH码的产生和特性分析的软件仿真。 3、掌握WALSH码的硬件产生方法。 (1, master code WALSH WALSH code generation principles and characteristics. 2, master WALSH code generation and characterization of the software simulation. 3, master code WALSH hardware generation approach.)

4、各个功能的主要源程序 1、移相模块： = 1 * GB2 * MERGEFORMAT ⑴、相位累加器： architecture one of add32 is begin   s

说明：  用VERILOG实现的，hdb3编码器和解码器，经过前仿真和后仿真成功(Achieved with the VERILOG, hdb3 encoder and decoder, after a successful pre-simulation and post simulation)