verilog_ad0809 cpld control

跑马灯-是移位寄存器 有6个灯，无延时entity-Bomadeng-shift register is a six lights, without delay entity

通过vhdl实现ls138硬件功能 通过vhdl实现ls138硬件功能 -the description of ls138 in vhdl

一个简单的探测110三位的探测器，用逻辑图和vhdl描述，包括实验报告和测试图。-a simple survey of 110 three detectors, and a logical map vhdl description, including reports and experimental test plan.

8位7段LED显示源码，扫描显示，稳定高效-seven of the eight LED source, scanning, stable and efficient

8位CPU软核设计与应用研究-8-bit CPU design and application of soft-core research .......

Altera的CycloneIII Start Board,使用的PFGA是3C25，包括原理图和PCB，用Cadence Allegro打开-Altera

16卫浮点FFT算法的VHDL实现，有测试文件。-16 floating-point FFT algorithm Wei VHDL realize, have the test paper.

FIR带通、带阻滤波器设计，需要输入截止频率以及容许偏差。(FIR band pass and band stop filter design)

说明：   基于VHDL语言数字秒表设计,在FPGA实验平台下开发(Digital stopwatch design based on VHDL, FPGA experimental platform under development)

JTAG design verilog code.