VHDL4人抢答器

n bit generic shift registers

fpga_sopc_enc28j60_tcp_ip_测试，源码程序包，本人测试通过！(Fpga_sopc_enc28j60_tcp_ip_ test, the source code packets, I test through!)

基于FPGA的uart控制器，波特率可选，VHDL编程，Quartusii 6.0 平台，vhdl语言编程-FPGA-based UART controller, an optional baud rate, VHDL programming, Quartusii 6.0 platform, vhdl language programming

altera DDR3 逻辑测试代码，这是工程实际调试好的代码，保证能用。(altera DDR3 vhdl code)

verilog实现UART收发功能，硬件平台为spartan 6，软件平台为ise14.7(verilog implement UART rx and tx function)

vhdl code for carry lookahead addder

频率计，ＶＥＲＩＬＯＧ代码，含详细　中文注释．-Cymometer, VERILOG code, containing a detailed Chinese Notes.

读取IGS数据中心提供的sinex文件 并恢复法方程(Read sinex file IGS data centers and to restore normal equation)

Spartan 3 Digilent Demo:This demo drives the perphrials on the Spartan 3 board. This drives a simple pattern to the VGA port, connects the switches to the LEDs, buttons to each anode of the seven segment decoder. The seven segment decoder has a simple counter running on it, and when SW0 is in the up position the seven segment decoder will display scan codes from the PS2 port. This demo how ever does not drive the RS-232 port or the memory. This is a simple design done entirely VHDL not microblaze.

Verilog code of SPI configurator for DAC AD7394 and AD7395