VHDL4人抢答器

说明：  fPGA中的竞争冒险现象的来源及其解决方法(FPGA in the source of the phenomenon of competitive risk-taking and their solutions)

本例为ADC0809接口电路VHDL程序原代码-The ADC0809 Interface Circuit Example for VHDL program source code

可用的24位x24位的booth乘法器的verilog代码(24X24 booth muplily)

说明：  qpsk的fpga实现，包含调制和解调部分，使用verilog语言(FPGA implementation of QPSK)

SDRAM基础性控制核 很有用的 VHDL状态机实现-SDRAM control of the nuclear basic useful VHDL state machine implementation

this file describes the steps in building a fifo buffer module in verilog hdl and programming them on an fpga device

DAC0832 接口电路程序.功能：产生频率为762.9Hz的锯齿波DAC0832VHDL程序与仿真-DAC0832 procedures interface circuit. Functions: generate the sawtooth frequency of 762.9Hz and simulation procedures DAC0832VHDL

利用matlab设计了一个切比雪夫滤波器，并且对滤波器性能进行了仿真分析。(Using the matlab design a chebyshev filter, and has carried on the simulation analysis on filter performance. )

对aurora模块时钟处理模块，实现时钟的分频等处理(Aurora module clock processing module,Clock frequency division and other processing)

XVRWARE Library Xilinx Inc. The XVRWARE Synthesis library provides macros and synthesis examples for constructing TMR circuits in VHDL for the Virtex architecture