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Baseband_line_code
基于VHDL语言的基带线路码产生电路设计(毕业论文),内涵完整的源代码(Based on VHDL language baseband line code generation circuit design (Thesis), meaning the complete source code)
- 2010-07-03 22:38:09下载
- 积分:1
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全加器的VHDL程序实现及仿真
全加器的VHDL程序实现及仿真-full adder VHDL simulation program and
- 2022-02-03 16:51:49下载
- 积分:1
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用VHDL实现一个四位十进制计数器来进行计数,并且仿真通过
用VHDL实现一个四位十进制计数器来进行计数,并且仿真通过-To use VHDL to achieve a 4 decimal counter to count, and the simulation through the
- 2022-06-18 07:56:39下载
- 积分:1
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1024point-fft--using-verilog-hdl
1024点快速傅里叶变换,使用verilog hdl硬件描述语言(1024point FFT,using verilog hdl)
- 2013-03-09 10:54:42下载
- 积分:1
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这是一个GPIB源程序代码,里面有硬件相对应的代码
这是一个GPIB源程序代码,里面有硬件相对应的代码-This is a GPIB source code, which corresponds to a hardware code
- 2022-02-15 23:31:46下载
- 积分:1
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clock
Quartus II软件设计数字电子钟,使用verilog语言编写各个
模块生成symbol files,再用原理图方式制作顶层文件。
完成的功能有:能够显示时、分、秒;具有清零,调节分钟的功能;
具有整点报时功能,声响电路发出叫声;
(failed to translate)
- 2013-05-07 10:11:31下载
- 积分:1
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bt656p
说明: BT656 时序, 逐行, 分辨率1280*960@25Hz(BT656 time series, row by row, resolution 1280*960@25Hz)
- 2020-12-09 12:09:19下载
- 积分:1
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crc循环冗余校验码,用于对传输信号进行编码校验,是信息更可靠...
crc循环冗余校验码,用于对传输信号进行编码校验,是信息更可靠-crc cyclic redundancy check code used to transmit coded signals to verify, the information is more reliable
- 2022-12-26 06:05:03下载
- 积分:1
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flashZ
FPGA控制m25p16flash芯片读写控制spi协议
可实现擦除写入读出功能(SPI protocol for read and write control of m25p16 flash chip controlled by FPGA
Erase Write-Read Function)
- 2018-12-19 16:10:59下载
- 积分:1
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ConvolutionWithViterbiDecoding
QPSK调制下的(5,7)卷积码的编码和维特比译码与BPSK调制下(5,7)卷积码的编码和维特比译码的BER特性(QPSK modulation under (5,7) convolutional code encoding and Viterbi decoding and BPSK modulation (5,7) convolutional code encoding and Viterbi BER characteristic)
- 2020-12-12 20:09:15下载
- 积分:1