USB的vhdl代码，具有很强的指导意义，对FPGA进行usb控制很有帮助！...

用Hspice实现一个三输入异或门，并分析其功耗和延时。(A three input XOR gate is implemented by Hspice, and its power consumption and delay are analyzed.)

完整的跑表设计，时，分，秒都显示，希望能对大家有用，谢啦(Complete stopwatch design, hours, minutes, seconds, show, hoping to be useful for everyone,)

基于延迟线的数字脉冲宽度调制，用于电力电子设备的触发信号产生(puls wide modulator based on delayline)

FPGA编写的三角波发生器，可以产生100HZ～500KHZ以上的三角波，波形稳定(FPGA prepared triangular wave generator, can produce more than 100HZ ~ 500KHZ triangle wave, waveform stability)

all funtions for a scale meter for maps in a 8051 microcontroler with an alphanumeric lcd display

初学verilog HDL时 找的好资料 大家共享-Beginners should try to find a good share information

URISC的RTL级设计，Verilog代码(Design: URISC RTL Verilog)

说明：  一种基于FPGA的调频连续波方位向多通道 FMCW SAR的实时成像信号处理方法及FPGA，包 括：步骤一、计算重构矩阵；步骤二、重构方位向 多通道数据，包括：步骤2 .1、对各个通道的回波 数据沿方位向分别间隔补零，并进行方位向傅里 叶变换；步骤2 .2、将方位向傅里叶变换之后各个 通道方位向相同位置的点组合为一个向量并与 重构矩阵相乘，得到重构完成的方位向数据；(An azimuth multichannel FMCW based on FPGA FMCW SAR real-time imaging signal processing method and FPGA, package Including: Step 1: calculate the reconstruction matrix; step 2: reconstruct the orientation Multichannel data, including: step 2.1, echo of each channel The data is compensated with zero along the azimuth direction respectively, and the azimuth Fourier is carried out Step 2.2, after the azimuth Fourier transform The points of the same position in the channel azimuth are combined into a vector and are connected withThe reconstruction matrix is multiplied to get the reconstructed azimuth data Step 2.3. Repeat step 2.3 for the data of different distance gates)

说明：  简单的单周期CPU设计，实现的指令有：算术运算指令、逻辑运算指令、移位指令、比较指令、存储器读/写指令、分支指令、跳转指令、停机指令。(Simple single-cycle CPU design,The instructions implemented are as follows:Arithmetic operation instruction, logical operation instruction, shift instruction, comparison instruction, memory read/write instruction, branch instruction, jump instruction, stop instruction.)

说明：  MATLAB to HDL Code conversion