USB的vhdl代码，具有很强的指导意义，对FPGA进行usb控制很有帮助！...

数控分频器的输出信号频率为输入数据的函数。用传统的方法设计,其设计过程和电路都比较复杂,且设计成 果的可修改性和可移植性都较差。基于VHDL 的数控分频器设计,整个过程简单、快捷,极易修改,可移植性强。他可利用 并行预置数的加法计数器和减法计数器实现。广泛应用于电子仪器、乐器等数字电子系统中。-NC divider output signal frequency is a function of input data. Using traditional methods of design, process and circuit design are complex and can modify the design of the results are poor and portability. NC VHDL divider based on the design, the whole process simple, fast, easy to modify, strong portability. He can use preset number of parallel addition and subtraction counter counter to achieve. Widely used in electronic equipment, musical instruments and other digital electronic systems.

是51单片机常用头文件定义，直接调用就可以，包括：1602液晶，12864液晶，5110屏，I2C,UART,精确延时函数，PWM调速，DS1302，DS18B20,,,,,,,(51 microcontroller used header file defines direct call can include: 1602 LCD, 12864 LCD, 5110 screen, I2C, UART, precision delay function PWM speed control, DS1302, DS18B20,,,,,)

VHDL implementation of RC6 encryption algorithm Test file represent applying all zero input and all zero key note that result is correct but bytes positions are swapped

说明：  实现数字频率合成实验，加载数据ram,形成波形(The experiment of digital frequency synthesis is realized, and the data RAM is loaded to form the waveform)

source vhdl code of D flipflop logic

Verilog 编写的串口通信模块 带测试代码(Verilog prepared by the serial communication module with a test code)

Pipeline processor verilog components

Universal Shift Register

四位拨妞开关作为输入，当输入值变化时将其转化成两位输出(The four DIP Niu switch as an input, when the input value changes, be converted into two output)

一个可综合的串并转换接口verilog源代码-a comprehensive series of conversion and interface Verilog source code