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VHDL常用源程序,希望以EDA技术学习者有用!
VHDL常用源程序,希望以EDA技术学习者有用!-VHDL source code commonly used, I hope to EDA technology learners useful!
- 2022-03-22 23:41:46下载
- 积分:1
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24小时计时时钟
实现24小时计时,因为位数不够,这里是12进位,可自行调整进位数(Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.)
- 2020-06-23 19:40:01下载
- 积分:1
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uaf42
使用uaf42设计的有源滤波器,高通滤波器的设计参数记录(Using uaf42 design active filters, high-pass filter design parameters recorded)
- 2012-09-09 21:49:49下载
- 积分:1
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在Quartus环境中,采用VHDL语言编写的出租车计费系统,系统共分为分频、状态切换、记程、计费等模块,模仿现实中出租车计费。...
在Quartus环境中,采用VHDL语言编写的出租车计费系统,系统共分为分频、状态切换、记程、计费等模块,模仿现实中出租车计费。-In the Quartus environment, the use of VHDL language taxi billing system, the system is divided into sub-frequency, state switching, recording process, billing and other modules, to imitate reality, taxi billing.
- 2022-02-25 18:59:33下载
- 积分:1
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multiplier.tar
用vhdl实现的booth算法乘法器,包含了multiplexer和rca adder,同时提供了一个测试文件,modelsim测试通过(Algorithm with a booth multiplier vhdl implementation, including a multiplexer and rca adder, while providing a test file, modelsim test pass)
- 2021-04-14 13:18:55下载
- 积分:1
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Matrix_inv
基于fpga的矩阵求逆运算,适用xilinx v6板卡(Inverse operation based on fpga matrix)
- 2017-04-24 09:55:13下载
- 积分:1
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在SOPC Builder的UART IP核接口
UART RS232 IPCORE for sopc builder
-RS232 UART IPCORE for sopc builder
- 2022-03-04 13:15:40下载
- 积分:1
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vsim
flii adder wave form 3
- 2015-04-27 20:02:44下载
- 积分:1
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verilog_show10
基于VHDL编写的10进制显示输出,基于16进制的10进制控制,适合初学者(VHDL-based display output written in decimal, hexadecimal, 10 hexadecimal-based control, suitable for beginners)
- 2011-11-21 14:29:56下载
- 积分:1
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verilog
lap of altera . it s basic about verilog
- 2010-06-25 20:30:32下载
- 积分:1