用VHDL写的

一些较为经典的VHDL代码,专注于信号分析与检测方面-Some of the more classic of the VHDL code, focusing on signal analysis and testing

verilog编程语言的讲解，有电子科技大学出版(verilog programming language to explain, there is the University of Electronic Science and Technology Publishing)

从MIC输入一段音频然后，再从AOUT的接口播放出来的verilog 的代码-Input from the MIC for some audio and then AOUT interface from broadcast in the Verilog code

等精度频率计的verilogHDL的实现,我花了好长时间才写的哦

我们的设计是用一个FSM控制器来控制发送什么命令，flash模块判断FSM发送过来的state信号来选择应该执行什么操作，当命令写入或者读出后，会发送一个flag_done命令，这个命令让我们判断上个指令是否完成，如果完成后FAM将发送下一个命令.(Our design uses a FSM controller to control what commands are sent. The flash module judges the state signal sent by the FSM to select what operation should be performed. When the command is written or read out, a flag_done command is sent. This command lets us judge whether the last word is finished or if the FAM will be sent after completion. The next command)

FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation

周立功Verilog HDL黄金参考指南，学习VerriLog的东西。-Golden Week Ligong Verilog HDL reference guide, learning VerriLog things.

说明：  基于FPGA的游戏实例，开发板为Xilinx的basys3，VGA显示(Basys3, VGA Display of Xilinx Development Board Based on Game Example of FPGA)

FPGA UART transmit and so on

vhdl的仿真 quartus 2的flv视频 -VHDL simulation of the flv video quartus 2