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qianzhaowang
一个简单的千兆以太网UDP协议的实现,可以实现数据的收发和ARP,实现PC端与FPGA的以太网通信(A simple implementation of Gigabit Ethernet UDP protocol can realize data sending and receiving and ARP, and realize Ethernet communication between PC and FPGA.)
- 2019-01-21 17:18:13下载
- 积分:1
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inverter chain
说明: 基于HSPICE实现的反相器链,并分析电路延时(Inverter chain based on HSPICE, and analyze circuit delay)
- 2020-04-21 12:55:52下载
- 积分:1
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该源码为几个正弦ROM,已经编译并通过,可以直接下载,不需要,内部含有正弦ROM表,还有ROM的宏模块...
该源码为几个正弦ROM,已经编译并通过,可以直接下载,不需要,内部含有正弦ROM表,还有ROM的宏模块-the source for several sine ROM, has been compiled and passed, can be directly downloaded, not internal ROM containing sine table, the Acer ROM module
- 2022-02-15 13:48:53下载
- 积分:1
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lowpass
低通滤波器(由matlab和simulink两种方法实现)源文件及图片示例(Low-pass filter) source file and photo examples (by the two methods matlab and simulink)
- 2013-03-13 18:36:40下载
- 积分:1
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24_Timer
说明: 使用Verilog编写的24位定时器,具有apb 总线接口,可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)
- 2021-04-27 21:38:44下载
- 积分:1
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zobrazenie_16_bit_cisla_paralel
16 bit switch input view in hexa format on 7seg display
- 2013-08-16 00:50:49下载
- 积分:1
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EDA
十进制计算机,实现十进制计数功能,简单可靠(vhdl)
- 2009-12-26 21:45:43下载
- 积分:1
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VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用
VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用-CARDBUS IP CORE
- 2022-03-12 11:28:40下载
- 积分:1
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time_echo
GPS接收机相关器中关于积分清零模块、历元计数模块、时钟模块、以及整个相关器(accumulator、epoch counter、time base、gps baseband)
- 2015-08-28 23:47:56下载
- 积分:1
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ds18b20Plcd
温度控制系统.运用ds18b20温度传感器将实时温度送入FPGA中,再将温度显示出来(Temperature control systems. Use ds18b20 temperature sensor into the FPGA in real-time temperature, then the temperature is displayed)
- 2014-04-27 18:39:30下载
- 积分:1