巴克内尔Verilog手册

宽带波束形成，设计FIR滤波器系数。带宽为500Hz--700Hz,采样率为3000Hz，对白噪声序列进行滤波，即得到有限带宽的宽带时域信号(Broadband beamforming design FIR filter coefficients. Bandwidth of 500Hz- 700Hz, sampling rate of 3000Hz, filtered white noise sequence, ie limited bandwidth broadband time domain signal)

Quartus II软件设计数字电子钟，使用verilog语言编写各个 模块生成symbol files，再用原理图方式制作顶层文件。 完成的功能有：能够显示时、分、秒；具有清零，调节分钟的功能； 具有整点报时功能，声响电路发出叫声； (failed to translate)

FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。(FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.)

基于verilog的1588V2协议的fpga实现，目前项目通用代码，供大家参考(Based on verilog 1588 v2 fpga implementation of the agreement, the project general code, for your reference)

logic lock 的vhdl源码，altera平台适用。-logic lock the VHDL source code, altera platform.

用VHDL语言在FPGA上实现了fft算法和fir滤波

片上网络NOC基于fpga实现的，routing模块。(NOC-chip networks realized fpga-based, routing module.)

正弦信号发生器，用VHDL来完成，抗干扰能力较强，(Sinusoidal signal generator, using VHDL to accomplish, a strong anti-interference ability,)

用VHDL语言实现了DES加密算法，其中包含了测试程序，能够进行仿真。(Using VHDL language implementation of the DES encryption algorithm, which contains the test procedures can be simulated.)

包括很多格式的85基准电路，不需手动转换，可以供学者自行选用。(This resource including many formats 85 banchmack circuit, without manual conversion, you can choose for the scholar.)