巴克内尔Verilog手册

用vhdl语言描写的存储器的读写，通俗易懂，简单实用。-Using VHDL language description of the memory read and write, user-friendly, simple and practical.

四位密码锁，移位显示，可以设置和更改密码。-4 lock, shift, it can be set up and change your password.

这是一个数字时钟的数字逻辑电路，整个工程打包上传，时钟可以计时、校时、整点报时、定时闹钟。使用电路图实现的。在quatarsII里面仿真的并且下载到DE2板上运行过。-This is a digital clock digital logic circuits, the whole project package upload, the clock could be time, school hours, the whole point timekeeping, timing alarm clock. The use of circuit implementation. The quatarsII inside the simulation, and downloaded to the DE2 board to run-off.

vhdl source code for 8 bit datapath logic

4位2选1多路选择器的设计与实现。nexy3开发板。本实验中用Verilog语句来描述。(Xilinx ISE 12.3.nexy3.)

ALTERA on chip fifo. this document is from altera. good resouce

四路控制抢答器模块设计 他的基本功能是，在四组参赛的情况下，首先抢答的发出抢答信号，此时其它抢答电路失去控制作用，在优先抢答的要在固定时间进行答题，否则直接扣一分

说明：  verilog讲义 卡内基梅陇大学verilog课程讲义-unlocked 卡内基梅陇大学verilog课程讲义-unlocked(Verilog Course Lectures at Carnegie Mellon, University Verilog Course Lectures at Carnegie Mellon University Verilog Course Lectures at Carnegie Mellon University)

VHDL的基本数学运算库,非常好用-VHDL basic arithmetic library, a very handy! !

可以直接用于工程应用的crc校验VHDL编码 里面有详细的规格书-Can be directly used for engineering applications of CRC checksum inside VHDL code has detailed specifications