利用VHDL语言编写的一个crc功能模块，可下载到FPGA实现功能

本例设计一个码率为500kb/s，字长为8 位、帧长为128 个字、帧同步码为EB90H 的PCM 采编器。用VHDL语言实现的。(This designs a code to lead for the 500 kbs|s, the word is long for 8, the growing is synchronous code of for 128 words and for the EB90 H of PCM adopt to weave a machine.Use what VHDL language carry out. )

URAT VHDL程序与仿真 URAT the VHDL program and Simulation (URAT the VHDL program and Simulation )

it shows bcd counter

用veriolg 语言编写的串口通讯程序，通过FPGA控制串口的通讯。(a veriog program completed on FPGA to contrlo a uart to communicaton with a computer )

一个7段的显示器，及按一定顺序循环得到的结果，可重复使用(A 7-segment display, and by a certain sequence and cycle the results obtained can be reused)

Verilog编程语言经典手册Classic Manual Verilog programming language(Verilog programming language classic manual Classic Manual Verilog programming language)

Am29LV160D数据基本知识手册，基本原理及工作方式。(Am29LV160D Data basic knowledge Manual, the basic principle and ways of working.)

由8 位加法器构成的以时序方式设计的8 位乘法器，采用逐项移位相加的方 法来实现相乘的VHDL程序代码。包含几个小模块和一个顶层设计文件，运行可用。(an 8 bit multiplier combined with 8 bit adder using a design by way of timing,and it use a way of Itemized shift to implement the multiply.It include some little module and a top level design document.)

本代码实现了输出移位寄存器功能，初学者可以借鉴学习-This code implements the output shift register functions, beginners can learn to learn

5对于进入密码锁的钥匙，假设复位后七节灯显示为" 0"，而使用sw1、sw2两个，则sw2-> sw1-> sw1-> sw2，则表示解锁右侧将导致七节灯显示为" 8"