cpu微命令vhdl源代码

这是自适应滤波器，使用verilog代码来编写的，已通过了仿真，效果很好。希望能给大家好好分享！(This adaptive filter verilog code to write, through a simulation, with good results. I hope to give a good share!)

VHDL 源码模块，可以实现最经典原PWM，可以用于电源，电机的控制()

七人抢答器 可做课程设计 能仿真 一人抢完其他人锁定-qiren qiangdaqi ke fangzhen

TEXIO study testbench passed VHDL FPGA CPLD simulation Altera quartus

用verilog编写的科斯塔斯环，希望有帮助(Costas loop written in verilog helpful)

说明：  本文研究的IIC总线控制器具有如下特征 1.兼容飞利浦I2C标准，以主机模式与外围设备进行数据通信，对IIC从机模型进行读/读，读/写，写/写，写/读[18]。 2.多主操作 3.软件可编程时钟频率 4.时钟拉伸和等待状态生成 5.软件可编程确认位 6.时钟同步设计 7.仲裁中断丢失，自动转移取消 8.开始/停止/重复启动检测/确认生成 9.总线忙检测(The IIC bus controller studied in this paper has the following characteristics. 1. Compatible with Philips I2C standard, data communication between host mode and peripheral devices, read/read, read/write, write/write, write/read for IIC slave model [18]. 2. Multiple Main Operations 3. Software programmable clock frequency 4. Clock stretching and waiting state generation 5. Software Programmable Confirmation Bit 6. Clock Synchronization Design 7. Loss of arbitration interruption and cancellation of automatic transfer 8. Start/Stop/Repeat Start Detection/Verification Generation 9. Bus busy detection)

开源软核处理器OpenRisc的SOPC设计

RS 编码和解码Verilog Code, 实现了RS（204,188)的编码和译码；(RS Coding and Decoding Verilog code，　implement RS（204,188) )

VerilogHDL_advanced_digital_design_code_Ch6 Verilog HDL 高级数字设计源码ch6(Advanced Digital Design VerilogHDL_advanced_digital_design_code_Ch6Verilog HDL source CH6)

自己编写的经过QuartusII验证的Verilog HDL程序，可以实现常见功能-After QuartusII their written procedures for verification of the Verilog HDL, can achieve common features