cpu微命令vhdl源代码

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is licensed under MIT License

uboot i2c driver code for arm a5 dual core cpu imapx820, which is an soc of infotmic.

VHDL设计的功能齐全的交通灯程序，经过仿真一切功能符合要求。-VHDL

vmm primer的使用使用文档，和之前vmm primer源代码配套使用！(vmm the primer use of the use of the document, and before supporting vmm the primer the source code to use!)

艾米电子的液晶1602的Verilog语言程序 (Amy e-LCD 1602 of the Verilog language program)

用键盘控制FPGA，再由FPGA控制VGA显示器是好东西-Use the keyboard to control FPGA, and then by the FPGA to control VGA display is a good thing

说明：  分数时延FIR滤波器FPGA设计的相关资料及软件无线电实验平台MFSS6842使用说明(Fractional delay FIR filter FPGA design related information and software radio experimental platform MFSS6842 instructions)

verilog spi file with testbench

FPGA，串口调试程序，接收模块，含FIFO IP核(FPGA uFF0C u4E32 u53E3 u8C03 u8BD5 u7A0B u5E8F uFF0C u63A5 u6536 u6A21 u5757 uFF0C u542BFIFO IP u6838)

基于FPGA的神经网络硬件实现中的关键问题研究，适合用fpga研究神经网络的工程人员参考(FPGA-based hardware implementation of neural networks in the study of key issues for research with neural networks fpga reference works)