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w5500_spi_fpga
共两个文件,一个是对网络芯片W5500进行控制的master spi接口,另一个是w5500命令控制逻辑,命令格式按照w5500芯片的要求,分为地址段,控制段和数据段进行统一控制。此外提供w5500芯片初始化及读写控制流程图。(A total of two documents, one is the master SPI interface for network control chip W5500, the other is a w5500 command control logic, command format in accordance with the requirement of w5500 chip, divided into address segment, unified control and data segments. In addition to provide w5500 chip initialization and read and write control flow chart.)
- 2020-06-26 14:00:02下载
- 积分:1
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基于FPGA的DDS程序代码
基于FPGA的DDS程序代码,实现的功能强大可以输正弦波,三角波,方波等波形,并且频率可以调节。实现对应的功能强大。(FPGA-based DDS program code can achieve powerful output sine wave, triangle wave, square wave waveform and frequency can be adjusted. Implement corresponding powerful.)
- 2015-09-15 23:09:00下载
- 积分:1
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红外
说明: 一个红外遥控,可以学习其他的红外编码,并存储记忆,并且将学习到的编码发送(An infrared remote control)
- 2020-06-25 10:27:32下载
- 积分:1
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HB1
说明: 半带滤波器,用于sigma-delta DAC中的设计(Half-band filter for sigma-delta DAC design)
- 2020-12-23 10:29:06下载
- 积分:1
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fskcodec
FSK编码器和译码器,有需要的朋友可以看看!(FSK encoder and decoder, there is a need friends can see!)
- 2014-08-11 21:12:06下载
- 积分:1
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clock
本程序实现数字钟系统,有整点报时功能,可显示切换年月日,定时功能(Digital clock system of this program, with the whole point timekeeping function, can display the date, the timing function)
- 2015-04-19 22:07:02下载
- 积分:1
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TCD1304_drive
FPGA驱动TCD1304AP线阵CCD,并经采集将数据通过串口传输至上位机(FPGA drives TCD1304AP linear CCD, and by collecting the data transmitted through the first bit machine serial)
- 2021-05-15 18:30:02下载
- 积分:1
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AD9767_DDS
说明: 基于fpga的DDS程序 可输出正弦波 方波 三角波 锯齿波(DDS program based on FPGA can output sinusoidal square wave triangular wave sawtooth wave)
- 2020-06-20 21:00:01下载
- 积分:1
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The experimental results are used to prepare MOSIN6 is achieved Verilog HDL lang...
有实验结果,用MOSIN6编写的,是Verilog HDL语言实现的.
练习三 利用条件语句实现计数分频时序电路
实验目的:
1. 掌握条件语句在简单时序模块设计中的使用;
2. 学习在Verilog模块中应用计数器;
3. 学习测试模块的编写、综合和不同层次的仿真。
练习四 阻塞赋值与非阻塞赋值的区别
实验目的:
1. 通过实验,掌握阻塞赋值与非阻塞赋值的概念和区别;
2. 了解阻塞赋值与非阻塞赋值的不同使用场合;
3. 学习测试模块的编写、综合和不同层次的仿真。
-The experimental results are used to prepare MOSIN6 is achieved Verilog HDL language. Practice the use of conditional statements to achieve the three sub-frequency timing circuit count experimental purposes: 1. Have conditional statements in the simple timing of the use of modular design 2. Learning modules in the Verilog Application of counter 3. to learn the preparation of the test module, integrated and different levels of simulation. Practicing the four blocking assignment with the distinction between non-blocking assignment experimental purposes: 1. Through experiments, hands blocking assignment with the concept of non-blocking assignment and distinction 2. Understanding of blocking and nonblocking assignment assignment usi
- 2022-03-18 15:26:04下载
- 积分:1
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ML605板子上的灯
ML605评估板上的流水灯,可以实现每隔0.16秒进行+1操作
#include
#include
#include
#include
#include
int main()
{
char a[] = "-100" ;
char b[] = "123" ;
int c ;
c = atoi( a ) + atoi( b ) ;
printf("c = %d
", c) ;
return 0;
- 2022-06-01 23:28:16下载
- 积分:1