Key_gen the Qutuas II v7.1 for sp1 invalid This is the v7.1 sp1 months key_gen

verilog lcd2864 适合初学者(verilog lcd2864 )

FPGA设计攻略及流程，包含时序收敛和引脚约束(FPGA design strategy and process, including time series convergence and pin constraints)

ad9983的检测视频信号的code及其project 用的是xilinx 的virtex4 但不包括I2C-ad9983 test video signal code and the project using a xilinx the virtex4 but does not include I2C

ULPI UTMI conversion

说明：  多通道连续声发射数据采集，每个通道最大5M，采用verilog编程，内部用状态机。(Multichannel continuous acoustic emission data acquisition, each channel up to 5M, using Verilog programming, internal state machine.)

说明：  基于FPGA的Veilog HDL实现代码，简单明了，希望能帮助verilog的初学者……(ＤＤＳ　based on Verilog ＤＨＬ for FPGA　)

这是一个verilog代码实现的常用乘法器。设计的是通用N比特乘M比特的二进制乘法器(This is a common multiplier verilog code. Design of a generic N bits by M bits of the binary multiplier)

这个文档回答了很多关于AHB总线在使用上经常遇到的问题(this doc gives a lot of answers for using AHB bus when doing design)

logic lock 的vhdl源码，altera平台适用。-logic lock the VHDL source code, altera platform.

说明：  FPGA测试程序，仅供测试硬件是否能够运行，主要功能是点亮运行指示灯(The main function of the test program of FPGA is to light the running indicator.)