Key_gen the Qutuas II v7.1 for sp1 invalid This is the v7.1 sp1 months key_gen

AD73311芯片的控制和数据程序，用于控制音频AD芯片。(AD73311 chip control and data program)

基于FPGA的成型滤波器的代码，里面内附激励文件，使用verilog编写(FPGA-based shaping filter code, which included incentives files using verilog write)

基于verilog convolutional coding 的卷积编码(verilog convolutional coding )

介绍了ＶＨＤＬ编程语言的基本语法，和一些编程实例-VHDL programming language introduced the basic grammar, and some programming examples

ANALYSIS OF ALL GATESS

Two-Dimensional Rank Order Filter Author: Gabor Szedo

说明：  基于fpga的verilog实现ad及uart，并进行仿真验证(Verilog based on FPGA implements AD and uart, and carries out simulation verification)

说明：  FPGA实现的AD采样控制程序的源码，欢迎大家下载(FPGA implementation of the AD sampling control)

axi_lite_user官方样例，精简功能，适用于zynq系列axi总线(Axi_lite_user official sample, streamline function, apply to zynq series Axi bus)

两个例子提醒我们如果我们要使用锁存器则不需要任何操作，如果我们想避免锁存器的话，我们要让这个元器件的每一个可能条件赋予一个值-signal or variable "" may not be assigned a new value in every possible path through the Process Statement