VHDL电子抢答器的实现。有多个文件，主控件是用图行实现。其余各功能模块用VHDL实现...

电子设计自动化中的计数器的实现程序，基于VHDL语言完成的-Electronic design automation in the realization of counter procedures, based on the VHDL language completed

用verilog编写在FLEX10K上实现的简易CPU-used in the preparation of Verilog FLEX10K achieve simple CPU

FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节，然后把它接收回来。 -FPGA development board to write the Verilog code: function is from the client computer sends a byte, and then receive it back.

VHDL子程序集,包括各种例程资料以及源码.-VHDL subprogram, including a variety of routine information as well as the source.

Arbiter code for simulation purpose

在altera公司FPGA上自己构建了一个最简单的niosii sopc系统(Altera FPGA company on its own to build a simple system niosii sopc)

mpeg-2 crcr32计算的代码，采用verilog编写，验证通过(mpeg-2 crcr32 caculate)

ps2 mouse controller

利用Cadence Allegro PCB SI进行SI仿真分析(Performed using the Cadence Allegro PCB SI SI simulation analysis)

基于VHDL的RS232通讯程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用(VHDL based on the RS232 communication procedures, including complete source code, locking pin, as well as download files documents can be directly downloaded using)