vhdl um teste com muita coisa interessante ae pra ver

说明：  canny 边缘检测基于梯度直方图的自适应阈值verilog实现(Canny edge detection based on gradient histogram adaptive threshold Verilog implementation)

2位并行加法器初学者必看初步了解FPGA-two count

这是一个基于Quartus2 开发环境的4输入加法器( 4adder basic on Quartus2)

实现QAM调制功能和QAM解调功能的代码.(Realize QAM modulation function and QAM demodulation function code.)

VHDL Code For Full Adder By Data Flow Modelling

fpga实验板上16*16点阵显示汉字的程序-翻译结果fpga实验板上16*16点阵显示汉字的程序(Experimental fpga board 16* 16 dot matrix display Chinese program- translation results fpga experimental board 16* 16 dot matrix display Chinese characters in the program)

design through verilog hdl

说明：  一个解决除法溢出的例子，可以学习到很多，注释很详细(A solution to the division overflow example, you can learn a lot, very detailed notes)

说明：  基于fpga的verilog实现ad及uart，并进行仿真验证(Verilog based on FPGA implements AD and uart, and carries out simulation verification)

Verilog HDL 写的SVPWM 算法的实现，使用的是altera 风暴系列的FPGA，占用资源1w+逻辑宏单元(Verilog HDL ，SVPWM)