ultractr源码，XPS技术，基于PPC平台

tms320c6747的测试程序 。用于dsp各个模块的测试，很好的例子(dsp tms320c6747)

rs422标准通讯模块 异步收发 verilog语言编写(rs422 standard communication module asynchronous receiver verilog language)

实现任意倍数的倍频,帮助大家解决VHDL倍频问题,(The realization of arbitrary multiples of the octave, octave VHDL help people solve problems,)

一个用VerilogHDL语言编写的模6的二进制计数器-a Verilog HDL language used in the preparation of the six-binary counter

FPGA UART transmit and so on

HDB3 encoder and decoder(HDB3 decoer)

USB接口控制器参考设计，xilinx提供的VHDL源代码-USB interface controller reference design for Xilinx VHDL source code

How to Connecting Xilinx FPGAs to the Philips

State.Machine.Coding.Styles.for.Synthesis（状态机，英文,VHDL）-State.Machine.Coding.Styles.for.Synthesis (FSM, English, VHDL)

根据软件无线电的思想，提出了一种新颖的数字信号处理算法，对QPSK信号的相位进行数字化处理，从而实现对QPSK信号的解调.该算法允许收发两端载波存在频差，用数字锁相实现收发端载波的同步，在频偏较大的情况下，估算频偏的大小，自适应设置环路的带宽，实现较短的捕获时间和较好的信噪性能。整个设计基于XILINX公司的ISE开发平台，并用Virtex-II系列FPGA实现。用FPGA实现调制解调器具有体积小、功耗低、集成度高、可软件升级、扰干扰能力强的特点，符合未来通信技术发展的方向。(According to the idea of software radio, a novel digital signal processing algorithm, the phase of QPSK digital signal processing, enabling the demodulation of QPSK signals. This algorithm allows the sending and receiving ends of the carrier frequency difference exists, using digital phase-locked to achieve synchronization of sending and receiving end of the carrier, in the case of large frequency offset, frequency offset estimation of the size, adaptive set the loop bandwidth to achieve shorter acquisition time and better noise performance. The whole design is based on the company XILINX ISE development platform, and Virtex-II series with the FPGA. FPGA realization of a modem with a small size, low power consumption, high integration, software upgrades available, the characteristics of strong interference interference, in line with the future direction of ICT development.)