Convolutional code encoder and Viterbi decoding to achieve

基于FPGA的图像采集卡的设计与相关说明-FPGA-based design of frame grabbers and related note

dual port ram control (dual port ram control dual port ram control dual port ram control)

Basic VHDL code to create a sine wave generator for an FPGA board.

用VERILOG编写的数字电子钟，用数码管进行显示时间-VERILOG prepared with digital electronic clock with a nixie tube display time

这是基于Nios II的12864液晶点亮程序，包含汉字、字符等(This is a program which is based on Nios II ,its function is light the 12864 LCD that including Chinese characters, characters)

Everspin SPI MRAM chipset(MR25H10,MR25H40,MR25H256)

VEROLOG的重要PPT资料,对初学者非常有益处-PPT important VEROLOG information is very useful for beginners

本源码详细介绍了UART的经典实例，敬请下载，谢谢适用-The source described in detail a classic example of UART, please download, Thank you apply

VHDL、Verilog HDL语言，是华为公司的技术指导书，希望对你有所帮助-VHDL、Verilog HDL

实现任意整数倍的信号分频，可调，不存在毛刺，波形完整，可运于信号的分析与检测(Arbitrary integer multiple of the signal frequency, adjustable, there is no glitch, waveform integrity, and can transport the analysis and the detection signal)