Convolutional code encoder and Viterbi decoding to achieve

基于VHDL语言，实现对ADC0809简单控制(Based on VHDL language, to achieve the ADC0809 simple control)

设计一个可供6组参赛选手使用的抢答器，具体要求如下：1)  可容纳6组参赛者的数字智能抢答器，每组设置一个抢答按钮供抢答者使用；2)  电路具有第一抢答信号的鉴别和锁存功能；3)  设置计分电路4)  设置犯规电路。顶层设计使用图形模块连线搭建，顶层功能模快均使用VHDL语言编写

10G高速以太网mac VERILOG源码 可仿真可实现(10G high speed Ethernet MAC verilog code can be used for synthesis or inplementation)

URISC 处理器由数据单元和控制单元组成。数据单元中包含保存运算数据和运算结果的数据寄存器，也包括用来完成数据运算的组合逻辑电路单元。控制单元用来产生控制信号序列，以决定何时进行何种数据运算。控制单元要从数据单元得到条件信号，以决定继续进行那些数据运算，数据单元要产生输出信号，数据运算状态等有用信息。-URISC processor by the data unit and control unit. Data unit included in the preservation of data and computing the results of computing the data register, but also data used to complete a combination of computing logic circuit unit. Control unit used to generate the control signal sequence, to determine when and what data computing. Control unit from the data unit received condition signal to determine the continuation of the data computation, data unit to produce output signals, data, such as computing the state of useful information.

The objective of this project is to design and implement the controller for an electronic safe. You will interface a 16-button keypad to the NIOS boards. The combination code of the safe will be the last

本代码可以用于产生正余弦信号波形，利用FPGA内部的ROM放置一个正余弦采样点的数据表格，通过循环取址的方法，实现波形连续输出。-This code can be used to generate positive cosine signal waveforms, using FPGA" s internal ROM to place a sampling point is the cosine of the data tables, the circulation method of taking the site to achieve a continuous output waveform.

用vhdl语言生成锯齿波，数据可自行改变(Sawtooth wave with vhdl language generation, the data can change by itself)

特权同学主讲的FPGA设计的时序约束专题（STA部分）(Speaker privileged classmates timing constraints for FPGA design topics (STA section))

多功能数字时钟 功能齐全 vhdl fp-Multi-functional digital clock vhdl fpaa

载波同步，costas环，基于Verilog的载波同步环(Carrier synchronization, costas ring, based on Verilog carrier synchronization ring )