vhdl adder with two input 4

无线通信中接收侧自动增益控制模块的vhdl代码实现(Receive side of the AGC module vhdl code for wireless communications)

This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by default in every Windows). Includes a testbench that takes an uncompressed PCM 16 bits Mono WAV file and outputs an IMA ADPCM compressed WAV file. Compression ratio is fixed for IMA-ADPCM, being 4:1. PLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Commons Attribution-Noncommercial-Share Alike 3.0 Unported). That means you may use it only for NON-COMMERCIAL purposes.

低密度校验码 ，很好用的代码，功能已经实现编码和译码(fpga ldpc)

这是一个简单的除法器（32bit/16bit),采用移位相减法-This is a simple divider (32bit/16bit), using phase shift subtraction

VHDL语言描述的二进制十进制译码电路，已经编译完成-Binary decimal decoder circuit

huffman transform in vhdl language

基于FPGA的可控100进制可逆计数器，运行环境maxplus(Controlled 100 hex reversible counter FPGA-based operating environment maxplus)

基于状态机的优秀SPI输出程序（以DAC7512为基础，可修改）(VHDL code about SPI)

Test for VHDL just a student version

基于FPGA的VERILOG语言的DS18B20温度检测程序，代码自测可用(FPGA based VERILOG language DS18B20 temperature detection program, code self test available)