vhdl adder with two input 4

4个7段lcd同时显示的程序，已经在digilent的nexy2板上通过验证，非常好用易懂，适合初学者学习-display 4 leds

ahb to apb master and slave

-- State machine for reading data from Dallas 1621 -- -- Testsystem for i2c controller--- State machine for reading data from Dall as 1621---- Testsystem for i2c controller

ANALYSIS OF ALL GATESS

数字频率计 FPGA 用verilog语言编写-Digital Cymometer verilog language used FPGA

(2,1,9)卷积编解码器，译码部分采用Vitebi译码算法，设计使用Verilog HDL语言，在Modelsim平台下仿真通过-(2,1,9) convolutional codec, decoding part decoding algorithm used Vitebi design using Verilog HDL language simulation in ModelSim platform through

RISC-DSP组合处理器设计优化[1].-RISC-DSP processor design portfolio optimization [1].

用于检测信号上升沿，输出与时钟相关的正脉冲(Detect the rising edge of the signal)

在Altera开发板上实现RS232串口通信，平台为CycloneII，可通过QuartusII软件修改引脚移植到其它平台(Realize RS232 serial communication on Altera development board, platform for CycloneII, through software QuartusII modify pin portable to other platforms)

3-8译码器地简单实现，采用QUARTUSii5.0环境编译-3-8 decoder to realize a simple, using the compiler QUARTUSii5.0 environment