vhdl adder with two input 4

浮点加法器的用Verilog实现，32位的浮点加法器(Floating point adder Verilog)

二进制除法器，采用移位相减的方法实现，位数可调-The source code of a divider

fsk调制与解调，此程序经过验证，可以运用，通讯方面的同学可以用-FSK modulation and demodulation, this procedure has been verified and can use communications students can use

初学verilog HDL时 找的好资料 大家共享-Beginners should try to find a good share information

说明：  PicoRV32 is a CPU core that implements the RISC-V RV32IMC Instruction Set. It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally contains a built-in interrupt controller. Tools (gcc, binutils, etc..) can be obtained via the RISC-V Website. The examples bundled with PicoRV32 expect various RV32 toolchains to be installed in /opt/riscv32i[m][c]. See the build instructions below for details.

坦克大战的演示程序 ，实现了基本的人机交互-Battle City demonstration program to achieve the basic human-computer interaction

一个8位的CPU设计，用verilog语言写的，希望有用(A CPU OF 8 BITS )

FPGA实现1553B编解码器功能 Verilog语言(FPGA implementation of 1553B codec function, Verilog language)

Design of a GF(64)-LDPC Decoder Based on the EMS Algorithm

ＡＤ转换代码，主要练习，没有具体的功能可以实现的，因为只是一部分(AD conversion code, practice, no specific function can be realized, because only part)