vhdl adder with two input 4

说明：  QPSK的解调程序，采用Verilog编写而成(QPSK demodulation program, written by Verilog)

attachement of attachments..bits pilani

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is licensed under MIT License

出租车计费，器设计一个出租车自动计费器，计费包括起步价、行车里程计费、停止和暂停不计费三部分。现场模拟汽车的启动、停止、暂停和换挡状态。分别用四位数码管显示金额和里程，各有两位小数，行程 3公里内，起步费为6元，超过3公里，以每公里1.3元计费(Car repair billing device)

combinational circuits code in vhdl

this is the vhdl code for the arithmetic logic unit.enjoy!

并串转换模块，内含有另个.vhd文件。一个是自己写的比较简单 另一个是参考的。-And the string conversion module, which contains another one. Vhd file. One is its relatively simple to write the other is the reference.

Lift Controller in vhdl using process statement and state disgram

EKG SIGNAL PROCESSING THROUGH CORDIC

《Verilog HDL 程序设计教程》9("Verilog HDL Design Guide" 9)