verilog 编写基于SRAM(CY7C1041)的代码

Based on the verilog such as frequency meter accuracy, except for measuring frequency can also measure pulse width of empty measure than 32 counts of data through the simulation SPI serial output to SCM processing and display

51单片机的下载器PCB图，可以用于at89cXX和at89c0xx系列的单片机的程序烧录，简单好用！使用proteus画的板。(51 MCU PCB map downloader, can be used at89cXX and procedures for microcontroller series at89c0xx burning, easy to use! Drawing board with proteus.)

三体模型仿真计算样例，基于特定的java浏览器插件对象，以非常形象的方式展示了三体运动物体的规律，可以调节运动参数，实时查看运动变化情况。

DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.(DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.)

floating point alignment

uart_tr 异步串口通信主机 使用verilog HDL语言编写(uart_tr the host of the uart )

verilog 实现的FFT 流水线操作，速度能达到200M(verilog pipelining the FFT implementation, the speed can reach 200M)

Clock Divider, divfactor of 18

高速ADC及DAC接口的参考设计。在Xilinx FPGA上实现。(Reference design of xapp1071.)

ALTERA NIOS处理器，VHDL语言在QUARTUS编译通过，然后有C语言在NIOS SHELL下驱动，实验音频解码-Altera NIOS processor, the QUARTUS VHDL compiler, then the C language under NIOS SHELL-driven, experimental audio decoder