登录
首页 » VHDL » With VHDL Design and Implementation of the multi

With VHDL Design and Implementation of the multi

于 2022-03-11 发布 文件大小:1.45 MB
0 168
下载积分: 2 下载次数: 1

代码说明:

用vhdl设计实现的多功能电子钟,可有日历,闹钟,修改等多种功能-With VHDL Design and Implementation of the multi-functional electronic bell, can have a calendar, alarm clock, to amend a variety of functions such as

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • TrackMe
    人的移动的跟踪,VERILOG实现,能跟踪人的画面移动(Tracking the movement of people, VERILOG realize that can track the person)
    2021-04-29 15:48:43下载
    积分:1
  • this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer u...
    this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural -this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural
    2022-05-22 09:03:05下载
    积分:1
  • 微波炉定时器集成电路的设计 1、 控制状态机:工作状态状态转换。 2、 数据装入电路:根据控制信号选择定时时间、测试数据或完成信号的装入。 3、...
    微波炉定时器集成电路的设计 1、 控制状态机:工作状态状态转换。 2、 数据装入电路:根据控制信号选择定时时间、测试数据或完成信号的装入。 3、 定时器电路:负责完成烹调过程中的时间递减计数和数据译码供给七段数码显示,同时还可以提供烹调完成时间的状态信号供控制状态机产生完成信号。 -microwave timer IC design a control state machine : state of the state conversion work. 2, data loading circuit : According to choose control signal timing, or the completion of the test data signal load. 3, timer circuit : responsible for the completion of the cooking process of counting and time decreasing supply data decoding digital paragraph 107, while cooking can also provide time to complete state control signal for the state machine generated signals.
    2022-04-02 09:49:26下载
    积分:1
  • tdc
    线性伸展TDC的verilog,包含门级网表(TDC linear stretch of verilog, includes gate-level netlist)
    2021-01-04 18:58:55下载
    积分:1
  • here is realized simple FIFO stack in vhdl. very simple example, but very help...
    here is realized simple FIFO stack in vhdl. very simple example, but very helpful.
    2022-03-12 07:44:59下载
    积分:1
  • DE2_Default
    基于DE2开发板的VGA显示模块,仅供大家参考(DE2 development board based on the VGA display module, for your reference)
    2008-07-21 16:12:32下载
    积分:1
  • Nios-II
    数字电路的设计。以软件方式实现硬件电路,功能强大,开发容易。(Digital circuit design. With software to realize the hardware circuit, powerful, development easy. )
    2011-12-03 09:47:56下载
    积分:1
  • 091655
    基于fpga的coms摄像头 扫描,参考文献,(Fpga based on the coms camera scan, reference literature,)
    2010-08-09 01:03:12下载
    积分:1
  • bt656p
    BT656 时序, 逐行, 分辨率1280*960@25Hz(BT656 time series, row by row, resolution 1280*960@25Hz)
    2020-12-09 12:09:19下载
    积分:1
  • lic_Xilinx_ISE_Vivado
    这是Xilinx ISE 14.X以及vivado、vivado_hls的license,亲测可用(Xilinx ISE 14.x vivado, vivado_hls license, pro-test available)
    2013-04-26 14:51:09下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载