With VHDL Design and Implementation of the multi

一种学习用的小程序，主要用与VHDL仿真的全加器的一段代码！大家可以下载进行修改于仿写-A learning to use a small program, mainly used with the VHDL simulation of a full-adder code! You can download the modified Yu Fang Xie

高速ADC及DAC接口的参考设计。在Xilinx FPGA上实现。(Reference design of xapp1071.)

An FPGA Implementation of a HoG-based Object Detection Processor

Hexadecimal to 7 segments

用verilog状态机实现的自动售货机，是一次课程作业，参考了网上的例子进行了修改(Automatic vending machine implemented with Verilog state machine)

本资源包括了加法器的VHDL代码实现，供大家学习。

Verilog实现的NOR FLASH控制器，基于M25P128开发，功能完整，简洁易懂，自用无问题。(Verilog implementations NOR FLASH controller, based M25P128 development, full-featured, easy to read, for personal use, no problem.)

该模块采用cordic算法计算正弦和余弦，并采用参数化方式实现。 ；包中存在其他模块。

采用FPGA实现的DDS波形发生器源码，可以实现频率幅值变换、正弦波、方波、三角波输出，输出频率可达1MHz(FPGA implementation of the DDS waveform generator source frequency amplitude transform, sine wave, square wave, triangle wave output, the output frequency up to 1MHz)

8b10b编码方式，verilog语言实现，有测试程序。能成功编码。没有环回验证，读者可自行编写环回验证测试程序。(8b10b encoding, verilog language, test procedures. Successful encoding. No loopback verification, readers can write your own loopback verification test procedures.)