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phone
用DE0开发板实现电话计费器,基本功能:可设置通话模式,能初始化话费余额,拨动开关可进入通话模式,并根据通话时间和相应通话模式扣除相应的费用。通话过程中能够通过开关切换显示通话时间和话费余额,并可暂停通话。压缩包里有详细的WORD文档的说明,包括波形仿真和DE0的引脚功能介绍。(Implemented by DE0 board telephone billing, basic function: to set the call mode, you can initiate credit balance, toggle switch into the talk mode, and deduct the cost of a call based on call time and the corresponding mode. Call talk time and can be displayed by switching credit balance, and mute. Compression bag has a detailed description of WORD documents, including the waveform simulation and DE0 pin function description.)
- 2020-11-06 13:19:49下载
- 积分:1
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VHDL程序讲解FIFO与RAM和ROM的数据交换
本资源详细的设计了一个FIFO的用法,将数据从ROM中读取送到FIFO缓存中然后RAM从FIFO缓存中读取数据存到内存中,改程序可以很好的学习三者之间的关系
- 2022-03-19 07:51:46下载
- 积分:1
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clock
说明: there's a clock divider for DE2 altra board clock (50MHz)
- 2017-07-29 23:46:29下载
- 积分:1
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九九乘法器
基于对ROM的编写,在quartusII上实现九九乘法器的实现,在试验箱的四个数码管上分别显示乘数,被乘数,积
- 2022-02-03 19:00:51下载
- 积分:1
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cordic-algorithm
codic algorithm,which is used to calculate triangular functions
- 2014-12-25 16:44:36下载
- 积分:1
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modbus_latest.tar
modbus的fpga实现。opencores上最新版本。使用fpga实现,可以大大提高响应速度,对其功能进行模块化。(modbus of fpga implementation. opencores the latest version. Use fpga implementation, can greatly improve the response speed, its function modularity.)
- 2020-10-22 10:37:23下载
- 积分:1
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运用vhdl程序设计语言进行ppm设计,ppm 设计在vhdl语言中非常常用,运用已经越来越广泛。...
运用vhdl程序设计语言进行ppm设计,ppm 设计在vhdl语言中非常常用,运用已经越来越广泛。-use vhdl program design language ppm design, vhdl ppm design in a very common language, has become increasingly widespread use.
- 2023-06-27 12:15:04下载
- 积分:1
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med_filter
基于图像处理的中值滤波VHDL源码,能够实现对图像的滤波(Based on the median filter VHDL source image processing, image filtering can be achieved)
- 2014-07-15 10:28:28下载
- 积分:1
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TOFED_TB_1
A 4 bit twisted ring counter is a sequential circuit which produces the following sequence of
output values: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001 and then repeats. Design a
circuit for a 4 bit twisted ring counter that uses four D flip flops. Draw a state transition
diagram, a state table and a schematic for your circuit. Design an alternate implementation
using just three flip flops and draw a state transition diagram, state table and a schematic
for your circuit. If your designs are extended to implement an n bit twisted ring counter,
how many flip flops are required using each of the two approaches. In what situations
would you prefer the first method? In what situations would you prefer the second?
- 2014-11-08 06:58:55下载
- 积分:1
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dianzhen
fpga实验板上16*16点阵显示汉字的程序-翻译结果fpga实验板上16*16点阵显示汉字的程序(Experimental fpga board 16* 16 dot matrix display Chinese program- translation results fpga experimental board 16* 16 dot matrix display Chinese characters in the program)
- 2013-12-24 16:28:00下载
- 积分:1