上海交通大学电子信息与电气工程学院VHDL经典教程

control stepper motor by fpga card with vhdl program

说明：  数字逻辑实验课第十二次作业，基于Verilog的Clock时钟(Clock based on Verilog)

一个可综合的同步FIFO的verilog源代码-An integrated synchronous FIFO in Verilog source code

随机数发生器

这个是DE2上的SDRAM 四个端口的驱动代码，相当实用！(This is a four-port SDRAM on a DE2 driver code, very useful!)

Verilog 经典实例，完整源码与大家分享-Verilog classic example of a complete source to share with you

Mentor Graphics ModelSim User s Guide Software v6.3g

this program get 20 point from user and draw functions.

用Verilog语言实现QPSK调制，QPSK是一种数字调制方式。它分为绝对相移和相对相移两种。 (Verilog language using QPSK modulation, QPSK is a digital modulation. It is divided into absolute and relative phase shift of the phase shift of two.)

数字秒表的实现，我还写个具体的过程要求等，(there is function of clock,it very useful)