并串转换模块，内含有另个.vhd文件。一个是自己写的比较简单 另一个是参考的。...

在Quartus环境中，采用VHDL语言编写的出租车计费系统，系统共分为分频、状态切换、记程、计费等模块，模仿现实中出租车计费。-In the Quartus environment, the use of VHDL language taxi billing system, the system is divided into sub-frequency, state switching, recording process, billing and other modules, to imitate reality, taxi billing.

说明：  单周期cpu，使用verilog编写的的单周期cpu支持......等功能(Single cycle CPU, using Verilog written single cycle CPU support... And other functions)

Altium Reference design for LMH0340 test bed and design

E1成帧器和解帧器的FPGA实现源码，测试可用(E1 Framer deframer)

美国人写的各种类型的fpag设计指导，非常详细的介绍了从fpga的型号，结构，实现，编程，等各个方面的要点。-Written by Americans of all types of fpag design guide, very detailed introduction from the FPGA models, structure, realize, programming, and other aspects of the main points.

使用VHDL编程的异步FIFO程序 经调试可运行-Using VHDL programming asynchronous FIFO procedure can be run by the debugger

基于Verilog的FPGA时钟分频程序(FPGA clock frequency division program based on Verilog)

DCT and Idct with vhdl and verilog

本程序实现两个整数平方和相加并且输出结果-the program two integers and the sum of squared output

这是8位微处理器的Verilog源代码，可以欠在Flex10k10里面-This is the 8-bit microprocessor Verilog source code, can they owed in Flex10k10