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FPGA_UART
用Verilog语言实现的FPGA UART独立收发模块
思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond.
功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。(Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA VERSA verified by the compiler Lattice Diamond. Features: Serial data is received immediately after the return, then every second serial port and then send the data+ 1.)
- 2011-10-03 13:18:56下载
- 积分：1
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CProgrammingforabsolutebeginners_WeLearnFree
ebook verilog HDL programming book
- 2015-12-04 14:39:40下载
- 积分：1
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suijitu
matlab随即图设计程序，应该比较有用，希望能申请会员成功吧。。(matlab then drawing design program)
- 2013-04-25 10:49:07下载
- 积分：1
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interr_timer0
interruption routine for PIC16F877
- 2009-12-30 00:43:05下载
- 积分：1
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Divider-vhdl
This is a divider, which is depicted as well.
It is a programming language Vhdl.
- 2013-09-29 18:28:11下载
- 积分：1
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rectifier
三相PWM整流，实现功率双向流动,可保持直流侧电压稳定(three-phase PWM rectifier, power can bidirectional flow ，can maintain the stable DC voltage)
- 2012-11-28 09:19:54下载
- 积分：1
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K9HCG08U1D K9PDG08U5D K9LBG08U0D K9MDG08U5D 三星 4G 8G 16G nand资料
K9HCG08U1D K9PDG08U5D K9LBG08U0D K9MDG08U5D 三星 4G 8G 16G nand资料-K9HCG08U1D K9PDG08U5D K9LBG08U0D K9MDG08U5D Samsung 4G 8G 16G nand datasheet
- 2022-01-28 16:21:35下载
- 积分：1
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RS2
该源代码是RS（31，19）码的完整编译码程序，采用的是VerilogHDL语言，包含了RS码的编码和译码，这蛋疼的东西花费好多时间(The source code is RS (31,19) code complete encoding and decoding procedures, and spend a lot of time using is VerilogHDL language contains the encoding and decoding of RS codes, this egg pain)
- 2012-09-09 13:04:41下载
- 积分：1
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bcd
it shows bcd counter
- 2013-01-01 16:16:48下载
- 积分：1
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5.7
设计一个简单的FIR滤波器，并按要求确定滤波器的系统函数。(Design a simple FIR filter, and determine the filter according to the requirement of system function.)
- 2015-04-17 18:26:49下载
- 积分：1
