通过本文章的学习能够使我们设计一些简单的逻辑电路和系统。很快我们就能过渡到设计相当复杂的数字逻辑系统。...

this is the source code we have been working on for our project using altera de2 board. the code can be run but some of it miss the end game module, while some doesn t have the complete vga code

一个简单的uvm搭建的ahb简单实例,包含了各个组件以及编译的运行的脚本(one sample example about ahb，include every component and compile script)

支持GF(2^n)域的rs编解码，可直接修改参数实现不同方式的RS编码和解码(This program is an encoder/decoder for Reed-Solomon codes.)

FPGA的经典例程，可以进行移植和借鉴使用(FPGA' s classic routines, can be transplanted and learn to use)

vhdl N-0.5分频方法设计，可以输入任意数值N，即分得到N－0.5的频率。-vhdl N- 0.5-frequency method, we can input arbitrary numerical N, namely, to be N- 0.5 frequencies.

本书通过100个实例，详细介绍便件描述语言vHDL的各种语法现象及其在专用集成电路(AHc)设计蝴还中的使用方法。(the book through one hundred examples, it detailed description language vHDL pieces of the phenomenon and its various grammatical in ASIC (AHc) were also designed butterfly The usage.)

Routine for I2C in VHDL

使用DDR3IP核进行仿真，写入读取数据(Using DDR3IP core to simulate, write and read data)

串口收发，实现可调波特率的串口通信，verilog源码(Serial port and transceiver)

In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear. and more sevear is such distortion is random. To handle this, multipath affected channels require Equalizers at receaver end. such equalizer uses different learning Algorithms for identifying channels continuously. This project is VHDL implementation of LMS learning algorithm with pipelined architecture. so this implementation can work with higher data rates with less clock speed requirments and so with less power consumpiton It uses Fixed point arithmatic blocks for filtering so suitable for coustom asic.