通过本文章的学习能够使我们设计一些简单的逻辑电路和系统。很快我们就能过渡到设计相当复杂的数字逻辑系统。...

是使用VHDL语言编写的基于FPGA的uart的源代码！-VHDL language is to use FPGA-based uart source code!

异步FIFO的设计 包括testbench 已调试成功-Asynchronous FIFO design includes testbench debug success has been

一个基于VerilogHDL语言的16位的booth算法的乘法器及其测试代码-VerilogHDL language based on the 16-bit multiplier of the booth algorithm and test code

Reed-solomon decoder, encoder design note

DDS Verilog 代码。包含英文文档说明-DDS Verilog code. Containing the English documentation

32位存储器Verilog附带test文件，可以在modulesim仿真 还有加法、减法器，译码器等常用Verilog器件，都附带仿真test。(Memory test with Verilog)

不错的verilog学习语言资料，详细地对verilog语言中的重要语句应用进行分析。(A good the verilog learn language information, verilog language statement application.)

第十章的代码。 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示(Chapter X code. This book by more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of additions device/counters, multipliers/dividers, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and the results demonstrate)

自己编的VHDL的波形发生器 做信号的可以-BOXING

TI DSP XDS100V3仿真器原理图Rev2.0(TI DSP XDS100V3 schematic Rev2.0)