Can realize the time digital clock display, and on the hours, minutes, seconds t...

VHDL硬件描述语言与数字逻辑电路设计-VHDL hardware description language and digital logic circuit design

VerilogHDL_advanced_digital_design_code_Ch6 Verilog HDL 高级数字设计源码ch6(Advanced Digital Design VerilogHDL_advanced_digital_design_code_Ch6Verilog HDL source CH6)

两位独立数码管100进制计数器，每1秒计数一次。从0到99，到99后又回到0.-Two independent 100-band digital tube counters, every time 1 seconds count. From 0 to 99, to 99 and then back to 0.

利用verilog HDL逐点比较法实现直线和圆弧插补(Use verilog HDL by-point comparison method to achieve linear and circular interpolation)

FPGA程序,使用Verilog语言生成1个脉冲可调的PPS脉冲信号。(FPGA program generates 1 PPS pulse signal, using Verilog language.)

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通信中加扰/解扰算法。FPGA源代码，verilogHDL语言实现，包含测试程序。(Perturbation/perturbation algorithm. FPGA source code, verilogHDL language implementation, including test procedures.)

直接频率合成，Quicklogic提供,部分源文件是Quicklogic 专用文件-direct frequency synthesis, pioneered provide some source document is dedicated ESP

Spartan® -3E 现场可编程门阵列家族是为满足对成本敏感的消费电子大量应用的需要 而特别设计的。 (Field Programmable Gate Array family needs is to meet the cost-sensitive applications, a large number of consumer electronics Specially designed.)

vhdl golden reference guide