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AVR_Core.tar
CPLD例程(语言)《Verilog HDL数字控制系统设计实例》AVR_Core.tar.gz-.rar(CPLDprogram dialogue /Verilog language design examples)
- 2011-11-12 20:43:49下载
- 积分:1
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FPGA
verilog编写的QPSK发射机的FPGA部分,已经过验证,完全达到要求。调制矢量误差4%(QPSK transmitter verilog prepared by the FPGA portion, has been proven, fully meet the requirements. Modulation vector error of 4 )
- 2013-10-08 14:58:23下载
- 积分:1
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Polyphase--Filter
多相抽取滤波器。分四相,两倍抽取,采用16阶FIR滤波器实现(Polyphase decimation filters. Divided into four phases, extracted twice using 16-order FIR filter implementation)
- 2020-09-10 15:58:02下载
- 积分:1
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1-Quadrature_decoder
说明: 光栅尺FPGA调试程序,本人亲自调试保证可用(Grating ruler FPGA debugging program)
- 2019-12-31 23:23:11下载
- 积分:1
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针对于Virtex5FPGA的DDR2读写测试的完整工程
资源描述针对于Virtex5FPGA的DDR2读写测试的完整工程,已测试可以使用,可以根据自己的ddr2配置自行更改。。。。
- 2023-02-19 21:40:05下载
- 积分:1
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convotion_decode
用verilog写的卷积码的编码程序以及viterbi译码程序(Use verilog write convolution code coding procedures and viterbi decoding program)
- 2012-09-06 20:24:55下载
- 积分:1
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CPU_Verilog
此代码完成了流水线CPU的设计。其中有ALU,控制模块,UART等verilog代码。(This code completes the design of pipelined CPU)
- 2017-07-06 19:45:33下载
- 积分:1
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usb_latest[1].tar
sub opercore USB CRC5 and CRC16 Modules ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/usb/(sub opercore USB CRC5 and CRC16 Modules//////////////////////// Author: Rudolf Usselmann//////// rudi@asics.ws//////////////////////// Downloaded from: http://www.opencores.org/cores/usb/)
- 2009-11-17 13:53:06下载
- 积分:1
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万能频率器,可以修改其中的参数,可是实现任意的分频!很方便!...
万能频率器,可以修改其中的参数,可是实现任意的分频!很方便!-Universal frequency, you can modify one of the parameters, but any implementation of the sub-band! Very convenient!
- 2022-01-26 04:43:16下载
- 积分:1
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bhas
this is a vhdl program...
- 2013-08-17 23:30:56下载
- 积分:1