Can realize the time digital clock display, and on the hours, minutes, seconds t...

这是一个verilog代码实现的常用乘法器。设计的是通用N比特乘M比特的二进制乘法器(This is a common multiplier verilog code. Design of a generic N bits by M bits of the binary multiplier)

并行读写14路串口数据，数据被写入FIFO，在收到读写信号后，SPI发送数据出去(Parallel read and write 14 serial port data, SPI send data)

基于fpga的实时视频采集与显示 高速化 小型化-fpga

design a clock using KIT DE1

说明：  lab report for lab 4

关于usb调试相关测试 代码，用于测试和适配等(usb coding for testing , verigy, for studing usb and fpga)

一个FIR低通滤波器,最小阻带衰减-30db,带内波动小于1db．用MAXPLUS2设计与仿真。-This is a FIR LPF, with-30dB in stop-band and sigma is less than 1dB. It is designed and simulated on MAXPLUS2.

HART 官方资料-HART协议采用基于Bell202标准的FSK频移键控信号，在低频的4-20mA模拟信号上叠加幅度为0.5mA的音频数字信号进行双向数字通讯，数据传输率为1.2kbps。(Official information-HART HART protocol based Bell202 standard frequency shift keying FSK signal at low frequencies 4-20mA analog signal amplitude is 0.5mA superimposed on the two-way audio digital signal digital communication, data transfer rate of 1.2kbps.)

说明：  环路滤波器是通信信号调制解调中最重要的一个部分，环路滤波器设计的好坏将直接影响到接收机的性能指标，二阶锁频辅助三阶锁相环路滤波器可以稳定跟踪具有加加速度的信号源，是现代通信中非常实用的技术，本文中详细编写了单载波信号产生模块、信道噪声模块、数字正交下变频模块、鉴频鉴相模块、环路滤波器模块，并包含了完整的testbench模块，对于初学者非常有用。(Loop filter is the most important part of communication signal modulation and demodulation. The design of loop filter will directly affect the performance index of receiver. The second-order frequency locking assisted third-order phase-locked loop filter can stably track the signal source with acceleration speed, which is a very practical technology in modern communication. In this paper, the single carrier signal generation module and channel noise are written in detail Sound module, digital orthogonal down conversion module, frequency and phase detection module, loop filter module, and contains a complete testbench module, which is very useful for beginners.)

我用FPGA来实现，这是一个出租车计价器，用来计算里程，我已在Quartus 2实现。(I used the FPGA to achieve, this is a taxi meter, calculate the mileage, I have been in quartus 2 to achieve.)